board/esd/meesc/meesc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  *
   7  * (C) Copyright 2009-2015
   8  * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
   9  * esd electronic system design gmbh <www.esd.eu>
  10  */
  11
  12 #include <common.h>
  13 #include <env.h>
  14 #include <init.h>
  15 #include <serial.h>
  16 #include <vsprintf.h>
  17 #include <asm/io.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-types.h>
  20 #include <asm/setup.h>
  21 #include <asm/arch/at91sam9_smc.h>
  22 #include <asm/arch/at91_common.h>
  23 #include <asm/arch/at91_pmc.h>
  24 #include <asm/arch/at91_rstc.h>
  25 #include <asm/arch/at91_matrix.h>
  26 #include <asm/arch/at91_pio.h>
  27 #include <asm/arch/clk.h>
  28 #include <netdev.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 /*
  33  * Miscelaneous platform dependent initialisations
  34  */
  35
  36 #ifdef CONFIG_REVISION_TAG
  37 static int hw_rev = -1; /* hardware revision */
  38
  39 int get_hw_rev(void)
  40 {
  41         if (hw_rev >= 0)
  42                 return hw_rev;
  43
  44         hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
  45         hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
  46         hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
  47         hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
  48
  49         if (hw_rev == 15)
  50                 hw_rev = 0;
  51
  52         return hw_rev;
  53 }
  54 #endif /* CONFIG_REVISION_TAG */
  55
  56 #ifdef CONFIG_CMD_NAND
  57 static void meesc_nand_hw_init(void)
  58 {
  59         unsigned long csa;
  60         at91_smc_t      *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
  61         at91_matrix_t   *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  62
  63         /* Enable CS3 */
  64         csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  65         writel(csa, &matrix->csa[0]);
  66
  67         /* Configure SMC CS3 for NAND/SmartMedia */
  68         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  69                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
  70                 &smc->cs[3].setup);
  71
  72         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  73                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  74                 &smc->cs[3].pulse);
  75
  76         writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
  77                 &smc->cs[3].cycle);
  78         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  79                 AT91_SMC_MODE_EXNW_DISABLE |
  80                 AT91_SMC_MODE_DBW_8 |
  81                 AT91_SMC_MODE_TDF_CYCLE(12),
  82                 &smc->cs[3].mode);
  83
  84         /* Configure RDY/BSY */
  85         gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  86
  87         /* Enable NandFlash */
  88         gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  89 }
  90 #endif /* CONFIG_CMD_NAND */
  91
  92 #ifdef CONFIG_MACB
  93 static void meesc_macb_hw_init(void)
  94 {
  95         at91_periph_clk_enable(ATMEL_ID_EMAC);
  96
  97         at91_macb_hw_init();
  98 }
  99 #endif
 100
 101 /*
 102  * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
 103  * controller debugging
 104  * The ET1100 is located at physical address 0x70000000
 105  * Its process memory is located at physical address 0x70001000
 106  */
 107 static void meesc_ethercat_hw_init(void)
 108 {
 109         at91_smc_t      *smc1   = (at91_smc_t *) ATMEL_BASE_SMC1;
 110
 111         /* Configure SMC EBI1_CS0 for EtherCAT */
 112         writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
 113                 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
 114                 &smc1->cs[0].setup);
 115         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
 116                 AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
 117                 &smc1->cs[0].pulse);
 118         writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
 119                 &smc1->cs[0].cycle);
 120         /*
 121          * Configure behavior at external wait signal, byte-select mode, 16 bit
 122          * data bus width, none data float wait states and TDF optimization
 123          */
 124         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
 125                 AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
 126                 AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
 127
 128         /* Configure RDY/BSY */
 129         at91_set_b_periph(AT91_PIO_PORTE, 20, 0);       /* EBI1_NWAIT */
 130 }
 131
 132 int dram_init(void)
 133 {
 134         /* dram_init must store complete ramsize in gd->ram_size */
 135         gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
 136                                 PHYS_SDRAM_SIZE);
 137         return 0;
 138 }
 139
 140 int dram_init_banksize(void)
 141 {
 142         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 143         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 144
 145         return 0;
 146 }
 147
 148 int board_eth_init(bd_t *bis)
 149 {
 150         int rc = 0;
 151 #ifdef CONFIG_MACB
 152         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
 153 #endif
 154         return rc;
 155 }
 156
 157 #ifdef CONFIG_DISPLAY_BOARDINFO
 158 int checkboard(void)
 159 {
 160         char str[32];
 161         u_char hw_type; /* hardware type */
 162
 163         /* read the "Type" register of the ET1100 controller */
 164         hw_type = readb(CONFIG_ET1100_BASE);
 165
 166         switch (hw_type) {
 167         case 0x11:
 168         case 0x3F:
 169                 /* ET1100 present, arch number of MEESC-Board */
 170                 gd->bd->bi_arch_number = MACH_TYPE_MEESC;
 171                 puts("Board: CAN-EtherCAT Gateway");
 172                 break;
 173         case 0xFF:
 174                 /* no ET1100 present, arch number of EtherCAN/2-Board */
 175                 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
 176                 puts("Board: EtherCAN/2 Gateway");
 177                 /* switch on LED1D */
 178                 at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
 179                 break;
 180         default:
 181                 /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
 182                 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
 183                 printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
 184                 puts("Board: EtherCAN/2 Gateway");
 185                 break;
 186         }
 187         if (env_get_f("serial#", str, sizeof(str)) > 0) {
 188                 puts(", serial# ");
 189                 puts(str);
 190         }
 191 #ifdef CONFIG_REVISION_TAG
 192         printf("\nHardware-revision: 1.%d\n", get_hw_rev());
 193 #endif
 194         printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
 195         return 0;
 196 }
 197 #endif /* CONFIG_DISPLAY_BOARDINFO */
 198
 199 #ifdef CONFIG_SERIAL_TAG
 200 void get_board_serial(struct tag_serialnr *serialnr)
 201 {
 202         char *str;
 203
 204         char *serial = env_get("serial#");
 205         if (serial) {
 206                 str = strchr(serial, '_');
 207                 if (str && (strlen(str) >= 4)) {
 208                         serialnr->high = (*(str + 1) << 8) | *(str + 2);
 209                         serialnr->low = simple_strtoul(str + 3, NULL, 16);
 210                 }
 211         } else {
 212                 serialnr->high = 0;
 213                 serialnr->low = 0;
 214         }
 215 }
 216 #endif
 217
 218 #ifdef CONFIG_REVISION_TAG
 219 u32 get_board_rev(void)
 220 {
 221         return hw_rev | 0x100;
 222 }
 223 #endif
 224
 225 #ifdef CONFIG_MISC_INIT_R
 226 int misc_init_r(void)
 227 {
 228         char            *str;
 229         char            buf[32];
 230         at91_pmc_t      *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 231
 232         /*
 233          * Normally the processor clock has a divisor of 2.
 234          * In some cases this this needs to be set to 4.
 235          * Check the user has set environment mdiv to 4 to change the divisor.
 236          */
 237         str = env_get("mdiv");
 238         if (str && (strcmp(str, "4") == 0)) {
 239                 writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
 240                         AT91SAM9_PMC_MDIV_4, &pmc->mckr);
 241                 at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
 242                 serial_setbrg();
 243                 /* Notify the user that the clock is not default */
 244                 printf("Setting master clock to %s MHz\n",
 245                         strmhz(buf, get_mck_clk_rate()));
 246         }
 247
 248         return 0;
 249 }
 250 #endif /* CONFIG_MISC_INIT_R */
 251
 252 int board_early_init_f(void)
 253 {
 254         at91_periph_clk_enable(ATMEL_ID_UHP);
 255
 256         return 0;
 257 }
 258
 259 int board_init(void)
 260 {
 261         /* initialize ET1100 Controller */
 262         meesc_ethercat_hw_init();
 263
 264         /* adress of boot parameters */
 265         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 266
 267 #ifdef CONFIG_CMD_NAND
 268         meesc_nand_hw_init();
 269 #endif
 270 #ifdef CONFIG_MACB
 271         meesc_macb_hw_init();
 272 #endif
 273 #ifdef CONFIG_AT91_CAN
 274         at91_can_hw_init();
 275 #endif
 276 #ifdef CONFIG_USB_OHCI_NEW
 277         at91_uhp_hw_init();
 278 #endif
 279         return 0;
 280 }