1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
7 * (C) Copyright 2009-2015
8 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
9 * esd electronic system design gmbh <www.esd.eu>
18 #include <asm/mach-types.h>
19 #include <asm/setup.h>
20 #include <asm/arch/at91sam9_smc.h>
21 #include <asm/arch/at91_common.h>
22 #include <asm/arch/at91_pmc.h>
23 #include <asm/arch/at91_rstc.h>
24 #include <asm/arch/at91_matrix.h>
25 #include <asm/arch/at91_pio.h>
26 #include <asm/arch/clk.h>
29 DECLARE_GLOBAL_DATA_PTR;
32 * Miscelaneous platform dependent initialisations
35 #ifdef CONFIG_REVISION_TAG
36 static int hw_rev = -1; /* hardware revision */
43 hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
44 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
45 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
46 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
53 #endif /* CONFIG_REVISION_TAG */
55 #ifdef CONFIG_CMD_NAND
56 static void meesc_nand_hw_init(void)
59 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
60 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
63 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
64 writel(csa, &matrix->csa[0]);
66 /* Configure SMC CS3 for NAND/SmartMedia */
67 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
68 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
71 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
72 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
75 writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
77 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
78 AT91_SMC_MODE_EXNW_DISABLE |
80 AT91_SMC_MODE_TDF_CYCLE(12),
83 /* Configure RDY/BSY */
84 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
86 /* Enable NandFlash */
87 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
89 #endif /* CONFIG_CMD_NAND */
92 static void meesc_macb_hw_init(void)
94 at91_periph_clk_enable(ATMEL_ID_EMAC);
101 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
102 * controller debugging
103 * The ET1100 is located at physical address 0x70000000
104 * Its process memory is located at physical address 0x70001000
106 static void meesc_ethercat_hw_init(void)
108 at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
110 /* Configure SMC EBI1_CS0 for EtherCAT */
111 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
112 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
114 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
115 AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
117 writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
120 * Configure behavior at external wait signal, byte-select mode, 16 bit
121 * data bus width, none data float wait states and TDF optimization
123 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
124 AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
125 AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
127 /* Configure RDY/BSY */
128 at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
133 /* dram_init must store complete ramsize in gd->ram_size */
134 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
139 int dram_init_banksize(void)
141 gd->bd->bi_dram[0].start = PHYS_SDRAM;
142 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
147 int board_eth_init(bd_t *bis)
151 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
156 #ifdef CONFIG_DISPLAY_BOARDINFO
160 u_char hw_type; /* hardware type */
162 /* read the "Type" register of the ET1100 controller */
163 hw_type = readb(CONFIG_ET1100_BASE);
168 /* ET1100 present, arch number of MEESC-Board */
169 gd->bd->bi_arch_number = MACH_TYPE_MEESC;
170 puts("Board: CAN-EtherCAT Gateway");
173 /* no ET1100 present, arch number of EtherCAN/2-Board */
174 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
175 puts("Board: EtherCAN/2 Gateway");
176 /* switch on LED1D */
177 at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
180 /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
181 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
182 printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
183 puts("Board: EtherCAN/2 Gateway");
186 if (env_get_f("serial#", str, sizeof(str)) > 0) {
190 #ifdef CONFIG_REVISION_TAG
191 printf("\nHardware-revision: 1.%d\n", get_hw_rev());
193 printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
196 #endif /* CONFIG_DISPLAY_BOARDINFO */
198 #ifdef CONFIG_SERIAL_TAG
199 void get_board_serial(struct tag_serialnr *serialnr)
203 char *serial = env_get("serial#");
205 str = strchr(serial, '_');
206 if (str && (strlen(str) >= 4)) {
207 serialnr->high = (*(str + 1) << 8) | *(str + 2);
208 serialnr->low = simple_strtoul(str + 3, NULL, 16);
217 #ifdef CONFIG_REVISION_TAG
218 u32 get_board_rev(void)
220 return hw_rev | 0x100;
224 #ifdef CONFIG_MISC_INIT_R
225 int misc_init_r(void)
229 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
232 * Normally the processor clock has a divisor of 2.
233 * In some cases this this needs to be set to 4.
234 * Check the user has set environment mdiv to 4 to change the divisor.
236 str = env_get("mdiv");
237 if (str && (strcmp(str, "4") == 0)) {
238 writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
239 AT91SAM9_PMC_MDIV_4, &pmc->mckr);
240 at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
242 /* Notify the user that the clock is not default */
243 printf("Setting master clock to %s MHz\n",
244 strmhz(buf, get_mck_clk_rate()));
249 #endif /* CONFIG_MISC_INIT_R */
251 int board_early_init_f(void)
253 at91_periph_clk_enable(ATMEL_ID_UHP);
260 /* initialize ET1100 Controller */
261 meesc_ethercat_hw_init();
263 /* adress of boot parameters */
264 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
266 #ifdef CONFIG_CMD_NAND
267 meesc_nand_hw_init();
270 meesc_macb_hw_init();
272 #ifdef CONFIG_AT91_CAN
275 #ifdef CONFIG_USB_OHCI_NEW