board/esd/meesc/meesc.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * (C) Copyright 2009-2015
   7  * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
   8  * esd electronic system design gmbh <www.esd.eu>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <asm/gpio.h>
  16 #include <asm/arch/at91sam9_smc.h>
  17 #include <asm/arch/at91_common.h>
  18 #include <asm/arch/at91_pmc.h>
  19 #include <asm/arch/at91_rstc.h>
  20 #include <asm/arch/at91_matrix.h>
  21 #include <asm/arch/at91_pio.h>
  22 #include <asm/arch/clk.h>
  23 #include <netdev.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 /*
  28  * Miscelaneous platform dependent initialisations
  29  */
  30
  31 #ifdef CONFIG_REVISION_TAG
  32 static int hw_rev = -1; /* hardware revision */
  33
  34 int get_hw_rev(void)
  35 {
  36         if (hw_rev >= 0)
  37                 return hw_rev;
  38
  39         hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
  40         hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
  41         hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
  42         hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
  43
  44         if (hw_rev == 15)
  45                 hw_rev = 0;
  46
  47         return hw_rev;
  48 }
  49 #endif /* CONFIG_REVISION_TAG */
  50
  51 #ifdef CONFIG_CMD_NAND
  52 static void meesc_nand_hw_init(void)
  53 {
  54         unsigned long csa;
  55         at91_smc_t      *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
  56         at91_matrix_t   *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  57
  58         /* Enable CS3 */
  59         csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  60         writel(csa, &matrix->csa[0]);
  61
  62         /* Configure SMC CS3 for NAND/SmartMedia */
  63         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  64                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
  65                 &smc->cs[3].setup);
  66
  67         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  68                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  69                 &smc->cs[3].pulse);
  70
  71         writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
  72                 &smc->cs[3].cycle);
  73         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  74                 AT91_SMC_MODE_EXNW_DISABLE |
  75                 AT91_SMC_MODE_DBW_8 |
  76                 AT91_SMC_MODE_TDF_CYCLE(12),
  77                 &smc->cs[3].mode);
  78
  79         /* Configure RDY/BSY */
  80         gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  81
  82         /* Enable NandFlash */
  83         gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  84 }
  85 #endif /* CONFIG_CMD_NAND */
  86
  87 #ifdef CONFIG_MACB
  88 static void meesc_macb_hw_init(void)
  89 {
  90         at91_periph_clk_enable(ATMEL_ID_EMAC);
  91
  92         at91_macb_hw_init();
  93 }
  94 #endif
  95
  96 /*
  97  * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
  98  * controller debugging
  99  * The ET1100 is located at physical address 0x70000000
 100  * Its process memory is located at physical address 0x70001000
 101  */
 102 static void meesc_ethercat_hw_init(void)
 103 {
 104         at91_smc_t      *smc1   = (at91_smc_t *) ATMEL_BASE_SMC1;
 105
 106         /* Configure SMC EBI1_CS0 for EtherCAT */
 107         writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
 108                 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
 109                 &smc1->cs[0].setup);
 110         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
 111                 AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
 112                 &smc1->cs[0].pulse);
 113         writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
 114                 &smc1->cs[0].cycle);
 115         /*
 116          * Configure behavior at external wait signal, byte-select mode, 16 bit
 117          * data bus width, none data float wait states and TDF optimization
 118          */
 119         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
 120                 AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
 121                 AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
 122
 123         /* Configure RDY/BSY */
 124         at91_set_b_periph(AT91_PIO_PORTE, 20, 0);       /* EBI1_NWAIT */
 125 }
 126
 127 int dram_init(void)
 128 {
 129         /* dram_init must store complete ramsize in gd->ram_size */
 130         gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
 131                                 PHYS_SDRAM_SIZE);
 132         return 0;
 133 }
 134
 135 int dram_init_banksize(void)
 136 {
 137         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 138         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 139
 140         return 0;
 141 }
 142
 143 int board_eth_init(bd_t *bis)
 144 {
 145         int rc = 0;
 146 #ifdef CONFIG_MACB
 147         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
 148 #endif
 149         return rc;
 150 }
 151
 152 #ifdef CONFIG_DISPLAY_BOARDINFO
 153 int checkboard(void)
 154 {
 155         char str[32];
 156         u_char hw_type; /* hardware type */
 157
 158         /* read the "Type" register of the ET1100 controller */
 159         hw_type = readb(CONFIG_ET1100_BASE);
 160
 161         switch (hw_type) {
 162         case 0x11:
 163         case 0x3F:
 164                 /* ET1100 present, arch number of MEESC-Board */
 165                 gd->bd->bi_arch_number = MACH_TYPE_MEESC;
 166                 puts("Board: CAN-EtherCAT Gateway");
 167                 break;
 168         case 0xFF:
 169                 /* no ET1100 present, arch number of EtherCAN/2-Board */
 170                 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
 171                 puts("Board: EtherCAN/2 Gateway");
 172                 /* switch on LED1D */
 173                 at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
 174                 break;
 175         default:
 176                 /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
 177                 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
 178                 printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
 179                 puts("Board: EtherCAN/2 Gateway");
 180                 break;
 181         }
 182         if (getenv_f("serial#", str, sizeof(str)) > 0) {
 183                 puts(", serial# ");
 184                 puts(str);
 185         }
 186 #ifdef CONFIG_REVISION_TAG
 187         printf("\nHardware-revision: 1.%d\n", get_hw_rev());
 188 #endif
 189         printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
 190         return 0;
 191 }
 192 #endif /* CONFIG_DISPLAY_BOARDINFO */
 193
 194 #ifdef CONFIG_SERIAL_TAG
 195 void get_board_serial(struct tag_serialnr *serialnr)
 196 {
 197         char *str;
 198
 199         char *serial = getenv("serial#");
 200         if (serial) {
 201                 str = strchr(serial, '_');
 202                 if (str && (strlen(str) >= 4)) {
 203                         serialnr->high = (*(str + 1) << 8) | *(str + 2);
 204                         serialnr->low = simple_strtoul(str + 3, NULL, 16);
 205                 }
 206         } else {
 207                 serialnr->high = 0;
 208                 serialnr->low = 0;
 209         }
 210 }
 211 #endif
 212
 213 #ifdef CONFIG_REVISION_TAG
 214 u32 get_board_rev(void)
 215 {
 216         return hw_rev | 0x100;
 217 }
 218 #endif
 219
 220 #ifdef CONFIG_MISC_INIT_R
 221 int misc_init_r(void)
 222 {
 223         char            *str;
 224         char            buf[32];
 225         at91_pmc_t      *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 226
 227         /*
 228          * Normally the processor clock has a divisor of 2.
 229          * In some cases this this needs to be set to 4.
 230          * Check the user has set environment mdiv to 4 to change the divisor.
 231          */
 232         if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
 233                 writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
 234                         AT91SAM9_PMC_MDIV_4, &pmc->mckr);
 235                 at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
 236                 serial_setbrg();
 237                 /* Notify the user that the clock is not default */
 238                 printf("Setting master clock to %s MHz\n",
 239                         strmhz(buf, get_mck_clk_rate()));
 240         }
 241
 242         return 0;
 243 }
 244 #endif /* CONFIG_MISC_INIT_R */
 245
 246 int board_early_init_f(void)
 247 {
 248         at91_periph_clk_enable(ATMEL_ID_PIOA);
 249         at91_periph_clk_enable(ATMEL_ID_PIOB);
 250         at91_periph_clk_enable(ATMEL_ID_PIOCDE);
 251         at91_periph_clk_enable(ATMEL_ID_UHP);
 252
 253         at91_seriald_hw_init();
 254
 255         return 0;
 256 }
 257
 258 int board_init(void)
 259 {
 260         /* initialize ET1100 Controller */
 261         meesc_ethercat_hw_init();
 262
 263         /* adress of boot parameters */
 264         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 265
 266 #ifdef CONFIG_CMD_NAND
 267         meesc_nand_hw_init();
 268 #endif
 269 #ifdef CONFIG_HAS_DATAFLASH
 270         at91_spi0_hw_init(1 << 0);
 271 #endif
 272 #ifdef CONFIG_MACB
 273         meesc_macb_hw_init();
 274 #endif
 275 #ifdef CONFIG_AT91_CAN
 276         at91_can_hw_init();
 277 #endif
 278 #ifdef CONFIG_USB_OHCI_NEW
 279         at91_uhp_hw_init();
 280 #endif
 281         return 0;
 282 }