ppc4xx: remove DU440 board
[platform/kernel/u-boot.git] / board / esd / hh405 / hh405.c
1 /*
2  * (C) Copyright 2001-2004
3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4  *
5  * (C) Copyright 2005
6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
7  *
8  * (C) Copyright 2006-2007
9  * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
10  *
11  * SPDX-License-Identifier:     GPL-2.0+
12  */
13
14 #include <common.h>
15 #include <asm/processor.h>
16 #include <asm/io.h>
17 #include <command.h>
18 #include <malloc.h>
19 #include <pci.h>
20 #include <sm501.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 /* FPGA internal regs */
25 #define FPGA_CTRL       ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x000))
26 #define FPGA_STATUS     ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x002))
27 #define FPGA_CTR        ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x004))
28 #define FPGA_BL         ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x006))
29
30 /* FPGA Control Reg */
31 #define FPGA_CTRL_REV0      0x0001
32 #define FPGA_CTRL_REV1      0x0002
33 #define FPGA_CTRL_VGA0_BL   0x0004
34 #define FPGA_CTRL_VGA0_BL_MODE 0x0008
35 #define FPGA_CTRL_CF_RESET  0x0040
36 #define FPGA_CTRL_PS2_PWR   0x0080
37 #define FPGA_CTRL_CF_PWRN   0x0100      /* low active */
38 #define FPGA_CTRL_CF_BUS_EN 0x0200
39 #define FPGA_CTRL_LCD_CLK   0x7000      /* mask for lcd clock */
40 #define FPGA_CTRL_OW_ENABLE 0x8000
41
42 #define FPGA_STATUS_CF_DETECT 0x8000
43
44 #ifdef CONFIG_VIDEO_SM501
45
46 #define SWAP32(x)        ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
47                           (((x) & 0x00ff0000) >>  8) | (((x) & 0xff000000) >> 24) )
48
49 #ifdef CONFIG_VIDEO_SM501_8BPP
50 #error CONFIG_VIDEO_SM501_8BPP not supported.
51 #endif /* CONFIG_VIDEO_SM501_8BPP */
52
53 #ifdef CONFIG_VIDEO_SM501_16BPP
54 #define BPP     16
55
56 /*
57  * 800x600 display B084SN03: PCLK = 40MHz
58  * => 2*PCLK = 80MHz
59  * 336/4 = 84MHz
60  * => PCLK = 84MHz
61  */
62 static const SMI_REGS init_regs_800x600 [] =
63 {
64 #if 1 /* test-only */
65         {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
66 #else
67         {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
68 #endif
69         {0x00004, SWAP32(0x00000000)},
70         /* clocks for pm1... */
71         {0x00048, SWAP32(0x00021807)},
72         {0x0004C, SWAP32(0x221a0a01)},
73         {0x00054, SWAP32(0x00000001)},
74         /* clocks for pm0... */
75         {0x00040, SWAP32(0x00021807)},
76         {0x00044, SWAP32(0x221a0a01)},
77         {0x00054, SWAP32(0x00000000)},
78         /* GPIO */
79         {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
80         /* panel control regs... */
81         {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
82         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
83         {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
84         {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
85         {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
86         {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
87         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
88         {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
89         {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
90         {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
91         {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
92         {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
93         {0x80200, SWAP32(0x00010000)}, /* crt display control */
94         {0, 0}
95 };
96
97 /*
98  * 1024x768 display G150XG02: PCLK = 65MHz
99  * => 2*PCLK = 130MHz
100  * 288/2 = 144MHz
101  * => PCLK = 72MHz
102  */
103 static const SMI_REGS init_regs_1024x768 [] =
104 {
105         {0x00004, SWAP32(0x00000000)},
106         /* clocks for pm1... */
107         {0x00048, SWAP32(0x00021807)},
108         {0x0004C, SWAP32(0x011a0a01)},
109         {0x00054, SWAP32(0x00000001)},
110         /* clocks for pm0... */
111         {0x00040, SWAP32(0x00021807)},
112         {0x00044, SWAP32(0x011a0a01)},
113         {0x00054, SWAP32(0x00000000)},
114         /* GPIO */
115         {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
116         /* panel control regs... */
117         {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
118         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
119         {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
120         {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
121         {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
122         {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
123         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
124         {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
125         {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
126         {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
127         {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
128         {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
129         {0x80200, SWAP32(0x00010000)}, /* crt display control */
130         {0, 0}
131 };
132
133 #endif /* CONFIG_VIDEO_SM501_16BPP */
134
135 #ifdef CONFIG_VIDEO_SM501_32BPP
136 #define BPP     32
137
138 /*
139  * 800x600 display B084SN03: PCLK = 40MHz
140  * => 2*PCLK = 80MHz
141  * 336/4 = 84MHz
142  * => PCLK = 84MHz
143  */
144 static const SMI_REGS init_regs_800x600 [] =
145 {
146 #if 0 /* test-only */
147         {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
148 #else
149         {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
150 #endif
151         {0x00004, SWAP32(0x00000000)},
152         /* clocks for pm1... */
153         {0x00048, SWAP32(0x00021807)},
154         {0x0004C, SWAP32(0x221a0a01)},
155         {0x00054, SWAP32(0x00000001)},
156         /* clocks for pm0... */
157         {0x00040, SWAP32(0x00021807)},
158         {0x00044, SWAP32(0x221a0a01)},
159         {0x00054, SWAP32(0x00000000)},
160         /* GPIO */
161         {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
162         /* panel control regs... */
163         {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
164         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
165         {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
166         {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
167         {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
168         {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
169         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
170         {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
171         {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
172         {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
173         {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
174         {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
175         {0x80200, SWAP32(0x00010000)}, /* crt display control */
176         {0, 0}
177 };
178
179 /*
180  * 1024x768 display G150XG02: PCLK = 65MHz
181  * => 2*PCLK = 130MHz
182  * 288/2 = 144MHz
183  * => PCLK = 72MHz
184  */
185 static const SMI_REGS init_regs_1024x768 [] =
186 {
187         {0x00004, SWAP32(0x00000000)},
188         /* clocks for pm1... */
189         {0x00048, SWAP32(0x00021807)},
190         {0x0004C, SWAP32(0x011a0a01)},
191         {0x00054, SWAP32(0x00000001)},
192         /* clocks for pm0... */
193         {0x00040, SWAP32(0x00021807)},
194         {0x00044, SWAP32(0x011a0a01)},
195         {0x00054, SWAP32(0x00000000)},
196         /* GPIO */
197         {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
198         /* panel control regs... */
199         {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
200         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
201         {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
202         {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
203         {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
204         {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
205         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
206         {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
207         {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
208         {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
209         {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
210         {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
211         {0x80200, SWAP32(0x00010000)}, /* crt display control */
212         {0, 0}
213 };
214
215 #endif /* CONFIG_VIDEO_SM501_32BPP */
216
217 #endif /* CONFIG_VIDEO_SM501 */
218
219 #if 0
220 #define FPGA_DEBUG
221 #endif
222
223 extern void lxt971_no_sleep(void);
224
225 /* fpga configuration data - gzip compressed and generated by bin2c */
226 const unsigned char fpgadata[] =
227 {
228 #include "fpgadata.c"
229 };
230
231 /*
232  * include common fpga code (for esd boards)
233  */
234 #include "../common/fpga.c"
235
236
237 /* logo bitmap data - gzip compressed and generated by bin2c */
238 unsigned char logo_bmp_320[] =
239 {
240 #include "logo_320_240_4bpp.c"
241 };
242
243 unsigned char logo_bmp_320_8bpp[] =
244 {
245 #include "logo_320_240_8bpp.c"
246 };
247
248 unsigned char logo_bmp_640[] =
249 {
250 #include "logo_640_480_24bpp.c"
251 };
252
253 unsigned char logo_bmp_1024[] =
254 {
255 #include "logo_1024_768_8bpp.c"
256 };
257
258
259 /*
260  * include common lcd code (for esd boards)
261  */
262 #include "../common/lcd.c"
263
264 #include "../common/s1d13704_320_240_4bpp.h"
265 #include "../common/s1d13705_320_240_8bpp.h"
266 #include "../common/s1d13806_640_480_16bpp.h"
267 #include "../common/s1d13806_1024_768_8bpp.h"
268
269
270 /*
271  * include common auto-update code (for esd boards)
272  */
273 #include "../common/auto_update.h"
274
275 au_image_t au_image[] = {
276         {"hh405/preinst.img", 0, -1, AU_SCRIPT},
277         {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
278         {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
279         {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
280         {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
281         {"hh405/postinst.img", 0, 0, AU_SCRIPT},
282 };
283
284 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
285
286
287 /*
288  * Get version of HH405 board from GPIO's
289  */
290 int board_revision(void)
291 {
292         unsigned long osrh_reg;
293         unsigned long isr1h_reg;
294         unsigned long tcr_reg;
295         unsigned long value;
296
297         /*
298          * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
299          */
300         osrh_reg = in_be32((void *)GPIO0_OSRH);
301         isr1h_reg = in_be32((void *)GPIO0_ISR1H);
302         tcr_reg = in_be32((void *)GPIO0_TCR);
303         out_be32((void *)GPIO0_OSRH, osrh_reg & ~0xC0003000);     /* output select */
304         out_be32((void *)GPIO0_ISR1H, isr1h_reg | 0xC0003000);    /* input select  */
305         out_be32((void *)GPIO0_TCR, tcr_reg & ~0x80400000);       /* select input  */
306
307         udelay(1000);            /* wait some time before reading input */
308         value = in_be32((void *)GPIO0_IR) & 0x80400000;         /* get config bits */
309
310         /*
311          * Restore GPIO settings
312          */
313         out_be32((void *)GPIO0_OSRH, osrh_reg);                   /* output select */
314         out_be32((void *)GPIO0_ISR1H, isr1h_reg);                 /* input select  */
315         out_be32((void *)GPIO0_TCR, tcr_reg);  /* enable output driver for outputs */
316
317         if (value & 0x80000000) {
318                 /* Revision 1.0 or 1.1 detected */
319                 return 1;
320         } else {
321                 if (value & 0x00400000) {
322                         /* unused */
323                         return 3;
324                 } else {
325                         return 2;
326                 }
327         }
328 }
329
330
331 int board_early_init_f (void)
332 {
333         /*
334          * IRQ 0-15  405GP internally generated; active high; level sensitive
335          * IRQ 16    405GP internally generated; active low; level sensitive
336          * IRQ 17-24 RESERVED
337          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
338          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
339          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
340          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
341          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
342          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
343          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
344          */
345         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
346         mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
347         mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
348         mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
349         mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
350         mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
351         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
352
353         /*
354          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
355          */
356         mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
357
358         return 0;
359 }
360
361 int cf_enable(void)
362 {
363         int i;
364
365         if (gd->board_type >= 2) {
366                 if (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT) {
367                         if (!(in_be16(FPGA_CTRL) & FPGA_CTRL_CF_BUS_EN)) {
368                                 out_be16(FPGA_CTRL,
369                                          in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_PWRN);
370
371                                 for (i=0; i<300; i++)
372                                         udelay(1000);
373
374                                 out_be16(FPGA_CTRL,
375                                          in_be16(FPGA_CTRL) | FPGA_CTRL_CF_BUS_EN);
376
377                                 for (i=0; i<20; i++)
378                                         udelay(1000);
379                         }
380                 } else {
381                         out_be16(FPGA_CTRL,
382                                  in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_BUS_EN);
383                         out_be16(FPGA_CTRL,
384                                  in_be16(FPGA_CTRL) | FPGA_CTRL_CF_PWRN);
385                 }
386         }
387
388         return 0;
389 }
390
391 int misc_init_r (void)
392 {
393         unsigned char *dst;
394         ulong len = sizeof(fpgadata);
395         int status;
396         int index;
397         int i;
398         char *str;
399         unsigned long contrast0 = 0xffffffff;
400
401         dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
402         if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
403                 printf ("GUNZIP ERROR - must RESET board to recover\n");
404                 do_reset (NULL, 0, 0, NULL);
405         }
406
407         status = fpga_boot(dst, len);
408         if (status != 0) {
409                 printf("\nFPGA: Booting failed ");
410                 switch (status) {
411                 case ERROR_FPGA_PRG_INIT_LOW:
412                         printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
413                         break;
414                 case ERROR_FPGA_PRG_INIT_HIGH:
415                         printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
416                         break;
417                 case ERROR_FPGA_PRG_DONE:
418                         printf("(Timeout: DONE not high after programming FPGA)\n ");
419                         break;
420                 }
421
422                 /* display infos on fpgaimage */
423                 index = 15;
424                 for (i=0; i<4; i++) {
425                         len = dst[index];
426                         printf("FPGA: %s\n", &(dst[index+1]));
427                         index += len+3;
428                 }
429                 putc ('\n');
430                 /* delayed reboot */
431                 for (i=20; i>0; i--) {
432                         printf("Rebooting in %2d seconds \r",i);
433                         for (index=0;index<1000;index++)
434                                 udelay(1000);
435                 }
436                 putc ('\n');
437                 do_reset(NULL, 0, 0, NULL);
438         }
439
440         puts("FPGA:  ");
441
442         /* display infos on fpgaimage */
443         index = 15;
444         for (i=0; i<4; i++) {
445                 len = dst[index];
446                 printf("%s ", &(dst[index+1]));
447                 index += len+3;
448         }
449         putc ('\n');
450
451         free(dst);
452
453         /*
454          * Reset FPGA via FPGA_INIT pin
455          */
456         /* setup FPGA_INIT as output */
457         out_be32((void *)GPIO0_TCR,
458                  in_be32((void *)GPIO0_TCR) | FPGA_INIT);
459         out_be32((void *)GPIO0_OR,
460                  in_be32((void *)GPIO0_OR) & ~FPGA_INIT);  /* reset low */
461         udelay(1000); /* wait 1ms */
462         out_be32((void *)GPIO0_OR,
463                  in_be32((void *)GPIO0_OR) | FPGA_INIT);   /* reset high */
464         udelay(1000); /* wait 1ms */
465
466         /*
467          * Write Board revision into FPGA
468          */
469         out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003));
470
471         /*
472          * Setup and enable EEPROM write protection
473          */
474         out_be32((void *)GPIO0_OR,
475                  in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
476
477         /*
478          * Reset touch-screen controller
479          */
480         out_be32((void *)GPIO0_OR,
481                  in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST);
482         udelay(1000);
483         out_be32((void *)GPIO0_OR,
484                  in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST);
485
486         /*
487          * Enable power on PS/2 interface (with reset)
488          */
489         out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR);
490         for (i=0;i<500;i++)
491                 udelay(1000);
492         out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR);
493
494         /*
495          * Get contrast value from environment variable
496          */
497         str = getenv("contrast0");
498         if (str) {
499                 contrast0 = simple_strtol(str, NULL, 16);
500                 if (contrast0 > 255) {
501                         printf("ERROR: contrast0 value too high (0x%lx)!\n",
502                                contrast0);
503                         contrast0 = 0xffffffff;
504                 }
505         }
506
507         /*
508          * Init lcd interface and display logo
509          */
510
511         str = getenv("bd_type");
512         if (strcmp(str, "ppc230") == 0) {
513                 /*
514                  * Switch backlight on
515                  */
516                 out_be16(FPGA_CTRL,
517                          in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL);
518                 out_be16(FPGA_BL, 0x0000);
519
520                 lcd_setup(1, 0);
521                 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
522                          regs_13806_1024_768_8bpp,
523                          sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
524                          logo_bmp_1024, sizeof(logo_bmp_1024));
525         } else if (strcmp(str, "ppc220") == 0) {
526                 /*
527                  * Switch backlight on
528                  */
529                 out_be16(FPGA_CTRL,
530                          in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL);
531                 out_be16(FPGA_BL, 0x0000);
532
533                 lcd_setup(1, 0);
534                 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
535                          regs_13806_640_480_16bpp,
536                          sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
537                          logo_bmp_640, sizeof(logo_bmp_640));
538         } else if (strcmp(str, "ppc215") == 0) {
539                 /*
540                  * Set default display contrast voltage
541                  */
542                 if (contrast0 == 0xffffffff) {
543                         out_be16(FPGA_CTR, 0x0082);
544                 } else {
545                         out_be16(FPGA_CTR, contrast0);
546                 }
547                 out_be16(FPGA_BL, 0xffff);
548                 /*
549                  * Switch backlight on
550                  */
551                 out_be16(FPGA_CTRL,
552                          in_be16(FPGA_CTRL) |
553                          FPGA_CTRL_VGA0_BL |
554                          FPGA_CTRL_VGA0_BL_MODE);
555                 /*
556                  * Set lcd clock (small epson)
557                  */
558                 out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250);
559                 udelay(100);               /* wait for 100 us */
560
561                 lcd_setup(0, 1);
562                 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
563                          regs_13705_320_240_8bpp,
564                          sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
565                          logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
566         } else if (strcmp(str, "ppc210") == 0) {
567                 /*
568                  * Set default display contrast voltage
569                  */
570                 if (contrast0 == 0xffffffff) {
571                         out_be16(FPGA_CTR, 0x0060);
572                 } else {
573                         out_be16(FPGA_CTR, contrast0);
574                 }
575                 out_be16(FPGA_BL, 0xffff);
576                 /*
577                  * Switch backlight on
578                  */
579                 out_be16(FPGA_CTRL,
580                          in_be16(FPGA_CTRL) |
581                          FPGA_CTRL_VGA0_BL |
582                          FPGA_CTRL_VGA0_BL_MODE);
583                 /*
584                  * Set lcd clock (small epson), enable 1-wire interface
585                  */
586                 out_be16(FPGA_CTRL,
587                          in_be16(FPGA_CTRL) |
588                          LCD_CLK_08330 |
589                          FPGA_CTRL_OW_ENABLE);
590
591                 lcd_setup(0, 1);
592                 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
593                          regs_13704_320_240_4bpp,
594                          sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
595                          logo_bmp_320, sizeof(logo_bmp_320));
596 #ifdef CONFIG_VIDEO_SM501
597         } else {
598                 pci_dev_t devbusfn;
599
600                 /*
601                  * Is SM501 connected (ppc221/ppc231)?
602                  */
603                 devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
604                 if (devbusfn != -1) {
605                         puts("VGA:   SM501 with 8 MB ");
606                         if (strcmp(str, "ppc221") == 0) {
607                                 printf("(800*600, %dbpp)\n", BPP);
608                                 out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */
609                         } else if (strcmp(str, "ppc231") == 0) {
610                                 printf("(1024*768, %dbpp)\n", BPP);
611                                 out_be16(FPGA_BL, 0x0000);
612                         } else {
613                                 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
614                                 return 0;
615                         }
616                 } else {
617                         printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
618                         return 0;
619                 }
620 #endif /* CONFIG_VIDEO_SM501 */
621         }
622
623         cf_enable();
624
625         return (0);
626 }
627
628
629 /*
630  * Check Board Identity:
631  */
632
633 int checkboard (void)
634 {
635         char str[64];
636         int i = getenv_f("serial#", str, sizeof(str));
637
638         puts ("Board: ");
639
640         if (i == -1) {
641                 puts ("### No HW ID - assuming HH405");
642         } else {
643                 puts(str);
644         }
645
646         if (getenv_f("bd_type", str, sizeof(str)) != -1) {
647                 printf(" (%s", str);
648         } else {
649                 puts(" (Missing bd_type!");
650         }
651
652         gd->board_type = board_revision();
653         printf(", Rev %ld.x)\n", gd->board_type);
654
655         return 0;
656 }
657
658 #ifdef CONFIG_IDE_RESET
659 void ide_set_reset(int on)
660 {
661         if (((gd->board_type >= 2) &&
662              (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT)) ||
663             (gd->board_type < 2)) {
664                 /*
665                  * Assert or deassert CompactFlash Reset Pin
666                  */
667                 if (on) {               /* assert RESET */
668                         cf_enable();
669                         out_be16(FPGA_CTRL,
670                                  in_be16(FPGA_CTRL) &
671                                  ~FPGA_CTRL_CF_RESET);
672                 } else {                /* release RESET */
673                         out_be16(FPGA_CTRL,
674                                  in_be16(FPGA_CTRL) |
675                                  FPGA_CTRL_CF_RESET);
676                 }
677         }
678 }
679 #endif /* CONFIG_IDE_RESET */
680
681
682 #if defined(CONFIG_SYS_EEPROM_WREN)
683 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
684  *         <state>     -1: deliver current state
685  *                     0: disable write
686  *                     1: enable write
687  *  Returns:           -1: wrong device address
688  *                      0: dis-/en- able done
689  *                   0/1: current state if <state> was -1.
690  */
691 int eeprom_write_enable (unsigned dev_addr, int state)
692 {
693         if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
694                 return -1;
695         } else {
696                 switch (state) {
697                 case 1:
698                         /* Enable write access, clear bit GPIO_SINT2. */
699                         out_be32((void *)GPIO0_OR,
700                                  in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
701                         state = 0;
702                         break;
703                 case 0:
704                         /* Disable write access, set bit GPIO_SINT2. */
705                         out_be32((void *)GPIO0_OR,
706                                  in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
707                         state = 0;
708                         break;
709                 default:
710                         /* Read current status back. */
711                         state = (0 == (in_be32((void *)GPIO0_OR) &
712                                        CONFIG_SYS_EEPROM_WP));
713                         break;
714                 }
715         }
716         return state;
717 }
718
719 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
720 {
721         int query = argc == 1;
722         int state = 0;
723
724         if (query) {
725                 /* Query write access state. */
726                 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
727                 if (state < 0) {
728                         puts ("Query of write access state failed.\n");
729                 } else {
730                         printf ("Write access for device 0x%0x is %sabled.\n",
731                                 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
732                         state = 0;
733                 }
734         } else {
735                 if ('0' == argv[1][0]) {
736                         /* Disable write access. */
737                         state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
738                 } else {
739                         /* Enable write access. */
740                         state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
741                 }
742                 if (state < 0) {
743                         puts ("Setup of write access state failed.\n");
744                 }
745         }
746
747         return state;
748 }
749
750 U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
751         "Enable / disable / query EEPROM write access",
752         ""
753 );
754 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
755
756
757 #ifdef CONFIG_VIDEO_SM501
758 #ifdef CONFIG_CONSOLE_EXTRA_INFO
759 /*
760  * Return text to be printed besides the logo.
761  */
762 void video_get_info_str (int line_number, char *info)
763 {
764         char str[64];
765         char str2[64];
766         int i = getenv_f("serial#", str2, sizeof(str));
767
768         if (line_number == 1) {
769                 sprintf(str, " Board: ");
770
771                 if (i == -1) {
772                         strcat(str, "### No HW ID - assuming HH405");
773                 } else {
774                         strcat(str, str2);
775                 }
776
777                 if (getenv_f("bd_type", str2, sizeof(str2)) != -1) {
778                         strcat(str, " (");
779                         strcat(str, str2);
780                 } else {
781                         strcat(str, " (Missing bd_type!");
782                 }
783
784                 sprintf(str2, ", Rev %ld.x)", gd->board_type);
785                 strcat(str, str2);
786                 strcpy(info, str);
787         } else {
788                 info [0] = '\0';
789         }
790 }
791 #endif /* CONFIG_CONSOLE_EXTRA_INFO */
792
793 /*
794  * Returns SM501 register base address. First thing called in the driver.
795  */
796 unsigned int board_video_init (void)
797 {
798         pci_dev_t devbusfn;
799         u32 addr;
800
801         /*
802          * Is SM501 connected (ppc221/ppc231)?
803          */
804         devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
805         if (devbusfn != -1) {
806                 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
807                 return (addr & 0xfffffffe);
808         }
809
810         return 0;
811 }
812
813 /*
814  * Returns SM501 framebuffer address
815  */
816 unsigned int board_video_get_fb (void)
817 {
818         pci_dev_t devbusfn;
819         u32 addr;
820
821         /*
822          * Is SM501 connected (ppc221/ppc231)?
823          */
824         devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
825         if (devbusfn != -1) {
826                 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
827                 addr &= 0xfffffffe;
828 #ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
829                 addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
830 #endif
831                 return addr;
832         }
833
834         return 0;
835 }
836
837 /*
838  * Called after initializing the SM501 and before clearing the screen.
839  */
840 void board_validate_screen (unsigned int base)
841 {
842 }
843
844 /*
845  * Return a pointer to the initialization sequence.
846  */
847 const SMI_REGS *board_get_regs (void)
848 {
849         char *str;
850
851         str = getenv("bd_type");
852         if (strcmp(str, "ppc221") == 0) {
853                 return init_regs_800x600;
854         } else {
855                 return init_regs_1024x768;
856         }
857 }
858
859 int board_get_width (void)
860 {
861         char *str;
862
863         str = getenv("bd_type");
864         if (strcmp(str, "ppc221") == 0) {
865                 return 800;
866         } else {
867                 return 1024;
868         }
869 }
870
871 int board_get_height (void)
872 {
873         char *str;
874
875         str = getenv("bd_type");
876         if (strcmp(str, "ppc221") == 0) {
877                 return 600;
878         } else {
879                 return 768;
880         }
881 }
882
883 #endif /* CONFIG_VIDEO_SM501 */
884
885
886 void reset_phy(void)
887 {
888 #ifdef CONFIG_LXT971_NO_SLEEP
889
890         /*
891          * Disable sleep mode in LXT971
892          */
893         lxt971_no_sleep();
894 #endif
895 }