3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include <asm/processor.h>
24 #include <asm/bitops.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
33 extern ulong flash_get_size (ulong base, int banknum);
35 int usbhub_init(void);
37 int eeprom_write_enable (unsigned dev_addr, int state);
38 int board_revision(void);
40 static int du440_post_errors;
42 int board_early_init_f(void)
45 u32 sdr0_pfc1, sdr0_pfc2;
48 mtdcr(EBC0_CFGADDR, EBC0_CFG);
49 mtdcr(EBC0_CFGDATA, 0xb8400000);
54 out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP);
55 out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP);
56 out_be32((void*)GPIO0_OSRL, 0x50055400);
57 out_be32((void*)GPIO0_OSRH, 0x55005000);
58 out_be32((void*)GPIO0_TSRL, 0x50055400);
59 out_be32((void*)GPIO0_TSRH, 0x55005000);
60 out_be32((void*)GPIO0_ISR1L, 0x50000000);
61 out_be32((void*)GPIO0_ISR1H, 0x00000000);
62 out_be32((void*)GPIO0_ISR2L, 0x00000000);
63 out_be32((void*)GPIO0_ISR2H, 0x00000000);
64 out_be32((void*)GPIO0_ISR3L, 0x00000000);
65 out_be32((void*)GPIO0_ISR3H, 0x00000000);
67 out_be32((void*)GPIO1_OR, 0x00000000);
68 out_be32((void*)GPIO1_TCR, 0xc2000000 |
69 CONFIG_SYS_GPIO1_IORSTN |
70 CONFIG_SYS_GPIO1_IORST2N |
71 CONFIG_SYS_GPIO1_LEDUSR1 |
72 CONFIG_SYS_GPIO1_LEDUSR2 |
73 CONFIG_SYS_GPIO1_LEDPOST |
74 CONFIG_SYS_GPIO1_LEDDU);
75 out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU);
76 out_be32((void*)GPIO1_OSRL, 0x0c280000);
77 out_be32((void*)GPIO1_OSRH, 0x00000000);
78 out_be32((void*)GPIO1_TSRL, 0xcc000000);
79 out_be32((void*)GPIO1_TSRH, 0x00000000);
80 out_be32((void*)GPIO1_ISR1L, 0x00005550);
81 out_be32((void*)GPIO1_ISR1H, 0x00000000);
82 out_be32((void*)GPIO1_ISR2L, 0x00050000);
83 out_be32((void*)GPIO1_ISR2H, 0x00000000);
84 out_be32((void*)GPIO1_ISR3L, 0x01400000);
85 out_be32((void*)GPIO1_ISR3H, 0x00000000);
88 * Setup the interrupt controller polarities, triggers, etc.
90 mtdcr(UIC0SR, 0xffffffff); /* clear all */
91 mtdcr(UIC0ER, 0x00000000); /* disable all */
92 mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
93 mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
94 mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
95 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
96 mtdcr(UIC0SR, 0xffffffff); /* clear all */
100 * bit30: ext. Irq 1: PLD : int 32+30
102 mtdcr(UIC1SR, 0xffffffff); /* clear all */
103 mtdcr(UIC1ER, 0x00000000); /* disable all */
104 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
105 mtdcr(UIC1PR, 0xfffffffd);
106 mtdcr(UIC1TR, 0x00000000);
107 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
108 mtdcr(UIC1SR, 0xffffffff); /* clear all */
112 * bit3: ext. Irq 2: DCF77 : int 64+3
114 mtdcr(UIC2SR, 0xffffffff); /* clear all */
115 mtdcr(UIC2ER, 0x00000000); /* disable all */
116 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
117 mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
118 mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
119 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
120 mtdcr(UIC2SR, 0xffffffff); /* clear all */
122 /* select Ethernet pins */
123 mfsdr(SDR0_PFC1, sdr0_pfc1);
124 mfsdr(SDR0_PFC2, sdr0_pfc2);
126 /* setup EMAC bridge interface */
127 if (board_revision() == 0) {
129 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
130 SDR0_PFC1_SELECT_CONFIG_1_2;
131 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
132 SDR0_PFC2_SELECT_CONFIG_1_2;
135 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
136 SDR0_PFC1_SELECT_CONFIG_6;
137 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
138 SDR0_PFC2_SELECT_CONFIG_6;
142 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
144 mtsdr(SDR0_PFC2, sdr0_pfc2);
145 mtsdr(SDR0_PFC1, sdr0_pfc1);
147 /* PCI arbiter enabled */
148 mfsdr(SDR0_PCI0, reg);
149 mtsdr(SDR0_PCI0, 0x80000000 | reg);
151 /* setup NAND FLASH */
152 mfsdr(SDR0_CUST0, sdr0_cust0);
153 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
154 SDR0_CUST0_NDFC_ENABLE |
155 SDR0_CUST0_NDFC_BW_8_BIT |
156 SDR0_CUST0_NDFC_ARE_MASK |
157 (0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) |
158 (0x80000000 >> (28 + CONFIG_SYS_NAND1_CS));
159 mtsdr(SDR0_CUST0, sdr0_cust0);
164 int misc_init_r(void)
169 unsigned long usb2d0cr = 0;
170 unsigned long usb2phy0cr, usb2h0cr = 0;
171 unsigned long sdr0_pfc1;
172 unsigned long sdr0_srst0, sdr0_srst1;
175 /* adjust flash start and offset */
176 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
177 gd->bd->bi_flashoffset = 0;
179 mtdcr(EBC0_CFGADDR, PB0CR);
180 pbcr = mfdcr(EBC0_CFGDATA);
181 size_val = ffs(gd->bd->bi_flashsize) - 21;
182 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
183 mtdcr(EBC0_CFGADDR, PB0CR);
184 mtdcr(EBC0_CFGDATA, pbcr);
187 * Re-check to get correct base address
189 flash_get_size(gd->bd->bi_flashstart, 0);
195 mfsdr(SDR0_PFC1, sdr0_pfc1);
196 mfsdr(SDR0_USB0, usb2d0cr);
197 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
198 mfsdr(SDR0_USB2H0CR, usb2h0cr);
200 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
201 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
202 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
203 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
204 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
205 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
206 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
207 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
208 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
209 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
211 /* An 8-bit/60MHz interface is the only possible alternative
212 when connecting the Device to the PHY */
213 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
214 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
216 /* To enable the USB 2.0 Device function through the UTMI interface */
217 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
219 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
220 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
222 mtsdr(SDR0_PFC1, sdr0_pfc1);
223 mtsdr(SDR0_USB0, usb2d0cr);
224 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
225 mtsdr(SDR0_USB2H0CR, usb2h0cr);
228 * Take USB out of reset:
229 * -Initial status = all cores are in reset
230 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
232 * -deassert reset to PHY
234 * -deassert reset to HOST
236 * -deassert all other resets
238 mfsdr(SDR0_SRST1, sdr0_srst1);
239 sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
240 SDR0_SRST1_P4OPB0 | \
242 SDR0_SRST1_PLB42OPB1 | \
243 SDR0_SRST1_OPB2PLB40);
244 mtsdr(SDR0_SRST1, sdr0_srst1);
247 mfsdr(SDR0_SRST1, sdr0_srst1);
248 sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
249 mtsdr(SDR0_SRST1, sdr0_srst1);
252 mfsdr(SDR0_SRST0, sdr0_srst0);
253 sdr0_srst0 &= ~SDR0_SRST0_USB2H;
254 mtsdr(SDR0_SRST0, sdr0_srst0);
257 /* finally all the other resets */
258 mtsdr(SDR0_SRST1, 0x00000000);
259 mtsdr(SDR0_SRST0, 0x00000000);
261 printf("USB: Host(int phy)\n");
264 * Clear PLB4A0_ACR[WRP]
265 * This fix will make the MAL burst disabling patch for the Linux
266 * EMAC driver obsolete.
268 reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
269 mtdcr(PLB4_ACR, reg);
273 * We have to wait at least 560ms until we may call usbhub_init
275 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
276 CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N);
279 * flash USR1/2 LEDs (600ms)
280 * This results in the necessary delay from IORST# until
281 * calling usbhub_init will succeed
283 for (j = 0; j < 3; j++) {
284 out_be32((void*)GPIO1_OR,
285 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) |
286 CONFIG_SYS_GPIO1_LEDUSR1);
288 for (i = 0; i < 100; i++)
291 out_be32((void*)GPIO1_OR,
292 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) |
293 CONFIG_SYS_GPIO1_LEDUSR2);
295 for (i = 0; i < 100; i++)
299 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
300 ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2));
311 int pld_revision(void)
313 out_8((void *)CONFIG_SYS_CPLD_BASE, 0x00);
314 return (int)(in_8((void *)CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
317 int board_revision(void)
319 int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK)
320 >> CONFIG_SYS_GPIO1_HWVER_SHIFT);
322 return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
323 ((rpins & 4) >> 1) | ((rpins & 8) >> 3);
326 #if defined(CONFIG_SHOW_ACTIVITY)
327 void board_show_activity (ulong timestamp)
329 if ((timestamp % 100) == 0)
330 out_be32((void*)GPIO1_OR,
331 in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1);
334 void show_activity(int arg)
337 #endif /* CONFIG_SHOW_ACTIVITY */
339 int du440_phy_addr(int devnum)
341 if (board_revision() == 0)
351 puts("Board: DU440");
353 if (getenv_r("serial#", serno, sizeof(serno)) > 0) {
358 printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
359 board_revision(), pld_revision());
363 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
364 void pci_master_init(struct pci_controller *hose)
366 unsigned short temp_short;
369 * Write the PowerPC440 EP PCI Configuration regs.
370 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
371 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
373 pci_read_config_word(0, PCI_COMMAND, &temp_short);
374 pci_write_config_word(0, PCI_COMMAND,
375 temp_short | PCI_COMMAND_MASTER |
378 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
380 int last_stage_init(void)
384 /* everyting is ok: turn on POST-LED */
385 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
387 /* slowly blink on errors and finally keep LED off */
388 for (e = 0; e < du440_post_errors; e++) {
389 out_be32((void*)GPIO1_OR,
390 in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
392 for (i = 0; i < 500; i++)
395 out_be32((void*)GPIO1_OR,
396 in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST);
398 for (i = 0; i < 500; i++)
405 #if defined(CONFIG_I2C_MULTI_BUS)
407 * read field strength from I2C ADC
409 int dcf77_status(void)
415 oldbus = I2C_GET_BUS();
418 if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
423 mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
429 int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
433 unsigned long long t1, t2;
439 printf("signal=%d mV\n", mv);
441 printf("ERROR - no signal\n");
444 pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
446 pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
447 if (pin && !pinold) { /* bit start */
449 if (t2 && ((unsigned int)(t1 - t2) /
450 (bd->bi_procfreq / 1000) >= 1800))
451 printf("Start of minute\n");
455 if (t1 && !pin && pinold) { /* bit end */
456 printf("%5d\n", (unsigned int)(get_ticks() - t1) /
457 (bd->bi_procfreq / 1000));
466 dcf77, 1, 1, do_dcf77,
467 "Check DCF77 receiver",
472 * initialize USB hub via I2C1
474 int usbhub_init(void)
479 uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
480 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
486 oldbus = I2C_GET_BUS();
489 for (reg = 0; reg < sizeof(u); reg++)
490 if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
497 if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
502 printf("initialized\n");
504 printf("failed - cannot initialize USB hub\n");
510 int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
516 hubinit, 1, 1, do_hubinit,
517 "Initialize USB hub",
520 #endif /* CONFIG_I2C_MULTI_BUS */
522 #define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
523 int boot_eeprom_write (unsigned dev_addr,
528 unsigned end = offset + cnt;
532 #if defined(CONFIG_SYS_EEPROM_WREN)
533 eeprom_write_enable(dev_addr, 1);
536 * Write data until done or would cross a write page boundary.
537 * We must write the address again when changing pages
538 * because the address counter only increments within a page.
541 while (offset < end) {
547 blk_off = offset & 0xFF; /* block offset */
549 addr[0] = offset >> 8; /* block number */
550 addr[1] = blk_off; /* block offset */
552 addr[0] |= dev_addr; /* insert device address */
557 * For a FRAM device there is no limit on the number of the
558 * bytes that can be ccessed with the single read or write
561 #if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
563 #define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
564 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
566 maxlen = BOOT_EEPROM_PAGE_SIZE -
567 BOOT_EEPROM_PAGE_OFFSET(blk_off);
569 maxlen = 0x100 - blk_off;
571 if (maxlen > I2C_RXTX_LEN)
572 maxlen = I2C_RXTX_LEN;
577 if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
583 #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
584 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
587 #if defined(CONFIG_SYS_EEPROM_WREN)
588 eeprom_write_enable(dev_addr, 0);
593 int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
598 if (!strcmp(argv[1], "533")) {
599 printf("Bootstrapping for 533MHz\n");
600 sdsdp[0] = 0x87788252;
601 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
602 sdsdp[1] = 0x095fa030;
603 sdsdp[2] = 0x40082350;
604 sdsdp[3] = 0x0d050000;
605 } else if (!strcmp(argv[1], "533-66")) {
606 printf("Bootstrapping for 533MHz (66MHz PCI)\n");
607 sdsdp[0] = 0x87788252;
608 /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
609 sdsdp[1] = 0x0957a030;
610 sdsdp[2] = 0x40082350;
611 sdsdp[3] = 0x0d050000;
612 } else if (!strcmp(argv[1], "667")) {
613 printf("Bootstrapping for 667MHz\n");
614 sdsdp[0] = 0x8778a256;
615 /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
616 sdsdp[1] = 0x0947a030;
617 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz
618 * -> not working when overclocking 533MHz chips
619 * -> untested on 667MHz chips */
620 /* sdsdp[1]=0x095fa030; */
621 sdsdp[2] = 0x40082350;
622 sdsdp[3] = 0x0d050000;
623 } else if (!strcmp(argv[1], "667-166")) {
624 printf("Bootstrapping for 667-166MHz\n");
625 sdsdp[0] = 0x8778a252;
626 sdsdp[1] = 0x09d7a030;
627 sdsdp[2] = 0x40082350;
628 sdsdp[3] = 0x0d050000;
631 printf("Bootstrapping for 533MHz (default)\n");
632 sdsdp[0] = 0x87788252;
633 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
634 sdsdp[1] = 0x095fa030;
635 sdsdp[2] = 0x40082350;
636 sdsdp[3] = 0x0d050000;
639 printf("Writing boot EEPROM ...\n");
640 if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
641 0, (uchar*)sdsdp, 16) != 0)
642 printf("boot_eeprom_write failed\n");
644 printf("done (dump via 'i2c md 52 0.1 10')\n");
649 sbe, 2, 0, do_setup_boot_eeprom,
654 #if defined(CONFIG_SYS_EEPROM_WREN)
656 * Input: <dev_addr> I2C address of EEPROM device to enable.
657 * <state> -1: deliver current state
660 * Returns: -1: wrong device address
661 * 0: dis-/en- able done
662 * 0/1: current state if <state> was -1.
664 int eeprom_write_enable (unsigned dev_addr, int state)
666 if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
667 (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr))
672 /* Enable write access, clear bit GPIO_SINT2. */
673 out_be32((void*)GPIO0_OR,
674 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP);
678 /* Disable write access, set bit GPIO_SINT2. */
679 out_be32((void*)GPIO0_OR,
680 in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP);
684 /* Read current status back. */
685 state = (0 == (in_be32((void*)GPIO0_OR) &
686 CONFIG_SYS_GPIO0_EP_EEP));
693 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
695 int query = argc == 1;
699 /* Query write access state. */
700 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
702 puts ("Query of write access state failed.\n");
704 printf ("Write access for device 0x%0x is %sabled.\n",
705 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
709 if ('0' == argv[1][0]) {
710 /* Disable write access. */
711 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
713 /* Enable write access. */
714 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
717 puts ("Setup of write access state failed.\n");
723 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
724 "Enable / disable / query EEPROM write access",
727 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
729 static int got_pldirq;
731 static int pld_interrupt(u32 arg)
733 int rc = -1; /* not for us */
734 u8 status = in_8((void *)CONFIG_SYS_CPLD_BASE);
736 /* check for PLD interrupt */
737 if (status & PWR_INT_FLAG) {
739 out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
741 got_pldirq = 1; /* trigger backend */
747 int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
751 /* clear any pending interrupt */
752 out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
754 irq_install_handler(CPLD_IRQ,
755 (interrupt_handler_t *)pld_interrupt, 0);
757 printf("Waiting ...\n");
759 /* Abort if ctrl-c was pressed */
766 printf("Got interrupt!\n");
767 printf("Power %sready!\n",
768 in_8((void *)CONFIG_SYS_CPLD_BASE) &
769 PWR_RDY ? "":"NOT ");
772 irq_free_handler(CPLD_IRQ);
776 wpi, 1, 1, do_waitpwrirq,
777 "Wait for power change interrupt",
782 * initialize DVI panellink transmitter
789 uchar u[] = {0x08, 0x34,
797 oldbus = I2C_GET_BUS();
800 for (i = 0; i < sizeof(u); i += 2)
801 if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
807 printf("initialized\n");
809 printf("failed - cannot initialize DVI transmitter\n");
815 int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
821 dviinit, 1, 1, do_dviinit,
822 "Initialize DVI Panellink transmitter",
827 * TODO: 'time' command might be useful for others as well.
828 * Move to 'common' directory.
830 int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
832 unsigned long long start, end;
833 char c, cmd[CONFIG_SYS_CBSIZE];
838 for (i = 1; i < argc; i++) {
844 while ((c = *p++) != '\0') {
851 ret = run_command (cmd, 0);
854 printf("ticks=%ld\n", (ulong)(end - start));
855 us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
856 printf("usec=%ld\n", us);
861 time, CONFIG_SYS_MAXARGS, 1, do_time,
862 "run command and output execution time",
866 extern void video_hw_rectfill (
867 unsigned int bpp, /* bytes per pixel */
868 unsigned int dst_x, /* dest pos x */
869 unsigned int dst_y, /* dest pos y */
870 unsigned int dim_x, /* frame width */
871 unsigned int dim_y, /* frame height */
872 unsigned int color /* fill color */
877 * draw rectangles using pseudorandom number generator
878 * (see http://www.embedded.com/columns/technicalinsights/20900500)
880 unsigned int rprime = 9972;
881 static unsigned int r;
882 static unsigned int Y;
884 unsigned int prng(unsigned int max)
886 if (r == 0 || r == 1 || r == -1)
887 r = rprime; /* keep from getting stuck */
889 r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
890 Y = (r >> 16) % max; /* choose upper bits and reduce */
894 int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
897 unsigned int x, y, dx, dy;
902 dx = prng(1280- x - 1);
903 dy = prng(1024 - y - 1);
904 color = prng(0x10000);
905 video_hw_rectfill(2, x, y, dx, dy, color);
911 gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo,