3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /*************************************************************************
25 * adaption for the Marvell DB64360 Board
26 * Ingo Assmus (ingo.assmus@keymile.com)
28 * adaption for the cpci750 Board
29 * Reinhard Arlt (reinhard.arlt@esd-electronics.com)
30 *************************************************************************/
33 /* sdram_init.c - automatic memory sizing */
37 #include "../../Marvell/include/memory.h"
38 #include "../../Marvell/include/pci.h"
39 #include "../../Marvell/include/mv_gen_reg.h"
44 #include "../../Marvell/common/i2c.h"
53 #endif /* of CONFIG_PCI */
61 int set_dfcdlInit(void); /* setup delay line of Mv64360 */
63 /* ------------------------------------------------------------------------- */
66 memory_map_bank(unsigned int bankNo,
67 unsigned int bankBase,
68 unsigned int bankLength)
77 printf("mapping bank %d at %08x - %08x\n",
78 bankNo, bankBase, bankBase + bankLength - 1);
80 printf("unmapping bank %d\n", bankNo);
84 memoryMapBank(bankNo, bankBase, bankLength);
87 for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
92 READ_LINE_AGGRESSIVE_PREFETCH |
93 READ_MULTI_AGGRESSIVE_PREFETCH |
97 pciMapMemoryBank(host, bankNo, bankBase, bankLength);
99 pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
102 pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
110 /* much of this code is based on (or is) the code in the pip405 port */
111 /* thanks go to the authors of said port - Josh */
113 /* structure to store the relevant information about an sdram bank */
114 typedef struct sdram_info {
116 uchar registered, ecc;
123 /* Typedefs for 'gtAuxilGetDIMMinfo' function */
125 typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE;
127 typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
128 SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
131 typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR;
132 typedef enum _max_CL_supported_SD {SD_CL_1=1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD;
135 /* SDRAM/DDR information struct */
136 typedef struct _gtMemoryDimmInfo
138 MEMORY_TYPE memoryType;
139 unsigned int numOfRowAddresses;
140 unsigned int numOfColAddresses;
141 unsigned int numOfModuleBanks;
142 unsigned int dataWidth;
143 VOLTAGE_INTERFACE voltageInterface;
144 unsigned int errorCheckType; /* ECC , PARITY..*/
145 unsigned int sdramWidth; /* 4,8,16 or 32 */;
146 unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */
147 unsigned int minClkDelay;
148 unsigned int burstLengthSupported;
149 unsigned int numOfBanksOnEachDevice;
150 unsigned int suportedCasLatencies;
151 unsigned int RefreshInterval;
152 unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */
153 unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns)*/
154 MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
155 MAX_CL_SUPPORTED_SD maxClSupported_SD;
156 unsigned int moduleBankDensity;
157 /* module attributes (true for yes) */
158 bool bufferedAddrAndControlInputs;
159 bool registeredAddrAndControlInputs;
161 bool bufferedDQMBinputs;
162 bool registeredDQMBinputs;
163 bool differentialClockInput;
164 bool redundantRowAddressing;
166 /* module general attributes */
167 bool suportedAutoPreCharge;
168 bool suportedPreChargeAll;
169 bool suportedEarlyRasPreCharge;
170 bool suportedWrite1ReadBurst;
171 bool suported5PercentLowVCC;
172 bool suported5PercentUpperVCC;
173 /* module timing parameters */
174 unsigned int minRasToCasDelay;
175 unsigned int minRowActiveRowActiveDelay;
176 unsigned int minRasPulseWidth;
177 unsigned int minRowPrechargeTime; /* measured in ns */
179 int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */
180 int addrAndCommandSetupTime; /* (measured in ns/100) */
181 int dataInputSetupTime; /* LoP left of point (measured in ns) */
182 int dataInputHoldTime; /* LoP left of point (measured in ns) */
183 /* tAC times for highest 2nd and 3rd highest CAS Latency values */
184 unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */
185 unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns)*/
186 unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */
187 unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns)*/
188 unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */
189 unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns)*/
191 unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */
192 unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns)*/
194 unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
195 unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns)*/
197 unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
198 unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns)*/
200 /* Parameters calculated from
201 the extracted DIMM information */
203 unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */
204 unsigned int numberOfDevices;
205 uchar drb_size; /* DRAM size in n*64Mbit */
206 uchar slot; /* Slot Number this module is inserted in */
207 uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */
209 uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */
210 uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */
211 uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */
212 unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */
213 unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */
214 unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */
215 uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */
222 * translate ns.ns/10 coding of SPD timing values
223 * into 10 ps unit values
225 static inline unsigned short
226 NS10to10PS(unsigned char spd_byte)
228 unsigned short ns, ns10;
230 /* isolate upper nibble */
231 ns = (spd_byte >> 4) & 0x0F;
232 /* isolate lower nibble */
233 ns10 = (spd_byte & 0x0F);
235 return(ns*100 + ns10*10);
239 * translate ns coding of SPD timing values
240 * into 10 ps unit values
242 static inline unsigned short
243 NSto10PS(unsigned char spd_byte)
245 return(spd_byte*100);
248 /* This code reads the SPD chip on the sdram and populates
249 * the array which is passed in with the relevant information */
250 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
252 check_dimm(uchar slot, AUX_MEM_DIMM_INFO *dimmInfo)
255 DECLARE_GLOBAL_DATA_PTR;
257 unsigned long spd_checksum;
259 uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
261 unsigned int i,j,density = 1,devicesForErrCheck = 0;
265 unsigned int rightOfPoint = 0,leftOfPoint = 0, mult, div, time_tmp;
266 int sign = 1,shift,maskLeftOfPoint,maskRightOfPoint;
267 uchar supp_cal, cal_val;
268 ulong memclk, tmemclk;
270 uchar trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks;
273 memclk = gd->bus_clk;
274 tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
276 memset(data, 0, sizeof(data));
281 DP(puts("before i2c read\n"));
283 ret = i2c_read(addr, 0, 2, data, 128);
285 DP(puts("after i2c read\n"));
287 if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd') || (data[67] != '-') ||
288 (data[68] != 'g') || (data[69] != 'm') || (data[70] != 'b') || (data[71] != 'h'))
293 if ((ret != 0) && (slot == 0))
295 memset(data, 0, sizeof(data));
296 data[ 0] = 0x80; data[ 1] = 0x08; data[ 2] = 0x07; data[ 3] = 0x0c;
297 data[ 4] = 0x09; data[ 5] = 0x01; data[ 6] = 0x48; data[ 7] = 0x00;
298 data[ 8] = 0x04; data[ 9] = 0x75; data[10] = 0x80; data[11] = 0x02;
299 data[12] = 0x80; data[13] = 0x10; data[14] = 0x08; data[15] = 0x01;
300 data[16] = 0x0e; data[17] = 0x04; data[18] = 0x0c; data[19] = 0x01;
301 data[20] = 0x02; data[21] = 0x20; data[22] = 0x00; data[23] = 0xa0;
302 data[24] = 0x80; data[25] = 0x00; data[26] = 0x00; data[27] = 0x50;
303 data[28] = 0x3c; data[29] = 0x50; data[30] = 0x32; data[31] = 0x10;
304 data[32] = 0xb0; data[33] = 0xb0; data[34] = 0x60; data[35] = 0x60;
305 data[64] = 'e' ; data[65] = 's' ; data[66] = 'd' ; data[67] = '-' ;
306 data[68] = 'g' ; data[69] = 'm' ; data[70] = 'b' ; data[71] = 'h' ;
310 /* zero all the values */
311 memset(dimmInfo, 0, sizeof(*dimmInfo));
313 /* copy the SPD content 1:1 into the dimmInfo structure*/
314 for(i = 0 ; i <= 127 ; i++)
316 dimmInfo->spd_raw_data[i] = data[i];
320 DP(printf("No DIMM in slot %d [err = %x]\n", slot, ret));
324 dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
326 #ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
328 for(i = 0 ; i <= 127 ; i++)
330 printf("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], data[i]);
335 /* find Manufactura of Dimm Module */
336 for(i = 0 ; i < sizeof(dimmInfo->manufactura) ; i++)
338 dimmInfo->manufactura[i] = data[64+i];
340 printf("\nThis RAM-Module is produced by: %s\n", dimmInfo->manufactura);
342 /* find Manul-ID of Dimm Module */
343 for(i = 0 ; i < sizeof(dimmInfo->modul_id) ; i++)
345 dimmInfo->modul_id[i] = data[73+i];
347 printf("The Module-ID of this RAM-Module is: %s\n", dimmInfo->modul_id);
349 /* find Vendor-Data of Dimm Module */
350 for(i = 0 ; i < sizeof(dimmInfo->vendor_data) ; i++)
352 dimmInfo->vendor_data[i] = data[99+i];
354 printf("Vendor Data of this RAM-Module is: %s\n", dimmInfo->vendor_data);
356 /* find modul_serial_no of Dimm Module */
357 dimmInfo->modul_serial_no = (*((unsigned long *)(&data[95])));
358 printf("Serial No. of this RAM-Module is: %ld (%lx)\n", dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
360 /* find Manufac-Data of Dimm Module */
361 dimmInfo->manufac_date = (*((unsigned int *)(&data[93])));
362 printf("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data [94]); /*dimmInfo->manufac_date*/
364 /* find modul_revision of Dimm Module */
365 dimmInfo->modul_revision = (*((unsigned int *)(&data[91])));
366 printf("Module Revision of this RAM-Module is: %d.%d\n", data[91], data [92]); /* dimmInfo->modul_revision*/
368 /* find manufac_place of Dimm Module */
369 dimmInfo->manufac_place = (*((unsigned char *)(&data[72])));
370 printf("manufac_place of this RAM-Module is: %d\n", dimmInfo->manufac_place);
373 /*------------------------------------------------------------------------------------------------------------------------------*/
374 /* calculate SPD checksum */
375 /*------------------------------------------------------------------------------------------------------------------------------*/
377 #if 0 /* test-only */
378 for(i = 0 ; i <= 62 ; i++)
380 spd_checksum += data[i];
383 if ((spd_checksum & 0xff) != data[63])
385 printf("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int)(spd_checksum & 0xff), data[63]);
390 printf("SPD Checksum ok!\n");
391 #endif /* test-only */
393 /*------------------------------------------------------------------------------------------------------------------------------*/
394 for(i = 2 ; i <= 35 ; i++)
398 case 2: /* Memory type (DDR / SDRAM) */
399 dimmInfo->memoryType = (data[i] == 0x7)? DDR:SDRAM;
401 if (dimmInfo->memoryType == 0)
402 DP(printf("Dram_type in slot %d is: SDRAM\n", dimmInfo->slot));
403 if (dimmInfo->memoryType == 1)
404 DP(printf("Dram_type in slot %d is: DDRAM\n", dimmInfo->slot));
407 /*------------------------------------------------------------------------------------------------------------------------------*/
409 case 3: /* Number Of Row Addresses */
410 dimmInfo->numOfRowAddresses = data[i];
411 DP(printf("Module Number of row addresses: %d\n", dimmInfo->numOfRowAddresses));
413 /*------------------------------------------------------------------------------------------------------------------------------*/
415 case 4: /* Number Of Column Addresses */
416 dimmInfo->numOfColAddresses = data[i];
417 DP(printf("Module Number of col addresses: %d\n", dimmInfo->numOfColAddresses));
419 /*------------------------------------------------------------------------------------------------------------------------------*/
421 case 5: /* Number Of Module Banks */
422 dimmInfo->numOfModuleBanks = data[i];
423 DP(printf("Number of Banks on Mod. : %d\n", dimmInfo->numOfModuleBanks));
425 /*------------------------------------------------------------------------------------------------------------------------------*/
427 case 6: /* Data Width */
428 dimmInfo->dataWidth = data[i];
429 DP(printf("Module Data Width: %d\n", dimmInfo->dataWidth));
431 /*------------------------------------------------------------------------------------------------------------------------------*/
433 case 8: /* Voltage Interface */
437 dimmInfo->voltageInterface = TTL_5V_TOLERANT;
438 DP(printf("Module is TTL_5V_TOLERANT\n"));
441 dimmInfo->voltageInterface = LVTTL;
442 DP(printf("Module is LVTTL\n"));
445 dimmInfo->voltageInterface = HSTL_1_5V;
446 DP(printf("Module is TTL_5V_TOLERANT\n"));
449 dimmInfo->voltageInterface = SSTL_3_3V;
450 DP(printf("Module is HSTL_1_5V\n"));
453 dimmInfo->voltageInterface = SSTL_2_5V;
454 DP(printf("Module is SSTL_2_5V\n"));
457 dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
458 DP(printf("Module is VOLTAGE_UNKNOWN\n"));
462 /*------------------------------------------------------------------------------------------------------------------------------*/
464 case 9: /* Minimum Cycle Time At Max CasLatancy */
465 shift = (dimmInfo->memoryType == DDR)? 4:2;
466 mult = (dimmInfo->memoryType == DDR)? 10:25;
467 maskLeftOfPoint = (dimmInfo->memoryType == DDR)? 0xf0:0xfc;
468 maskRightOfPoint = (dimmInfo->memoryType == DDR)? 0xf:0x03;
469 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
470 rightOfPoint = (data[i] & maskRightOfPoint)* mult;
471 dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = leftOfPoint;
472 dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = rightOfPoint;
473 DP(printf("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n",leftOfPoint, rightOfPoint));
475 /*------------------------------------------------------------------------------------------------------------------------------*/
477 case 10: /* Clock To Data Out */
478 div = (dimmInfo->memoryType == DDR)? 100:10;
479 time_tmp = (((data[i] & 0xf0) >> 4)*10) + ((data[i] & 0x0f));
480 leftOfPoint = time_tmp / div;
481 rightOfPoint = time_tmp % div;
482 dimmInfo->clockToDataOut_LoP = leftOfPoint;
483 dimmInfo->clockToDataOut_RoP = rightOfPoint;
484 DP(printf("Clock To Data Out: %d.%2d [ns]\n",leftOfPoint, rightOfPoint ));
485 /*dimmInfo->clockToDataOut*/
487 /*------------------------------------------------------------------------------------------------------------------------------*/
490 case 11: /* Error Check Type */
491 dimmInfo->errorCheckType = data[i];
492 DP(printf("Error Check Type (0=NONE): %d\n", dimmInfo->errorCheckType));
495 /*------------------------------------------------------------------------------------------------------------------------------*/
497 case 12: /* Refresh Interval */
498 dimmInfo->RefreshInterval = data[i];
499 DP(printf("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", dimmInfo->RefreshInterval));
501 /*------------------------------------------------------------------------------------------------------------------------------*/
503 case 13: /* Sdram Width */
504 dimmInfo->sdramWidth = data[i];
505 DP(printf("Sdram Width: %d\n", dimmInfo->sdramWidth));
507 /*------------------------------------------------------------------------------------------------------------------------------*/
509 case 14: /* Error Check Data Width */
510 dimmInfo->errorCheckDataWidth = data[i];
511 DP(printf("Error Check Data Width: %d\n", dimmInfo->errorCheckDataWidth));
513 /*------------------------------------------------------------------------------------------------------------------------------*/
515 case 15: /* Minimum Clock Delay */
516 dimmInfo->minClkDelay = data[i];
517 DP(printf("Minimum Clock Delay: %d\n", dimmInfo->minClkDelay));
519 /*------------------------------------------------------------------------------------------------------------------------------*/
521 case 16: /* Burst Length Supported */
522 /******-******-******-*******
523 * bit3 | bit2 | bit1 | bit0 *
524 *******-******-******-*******
525 burst length = * 8 | 4 | 2 | 1 *
526 *****************************
528 If for example bit0 and bit2 are set, the burst
529 length supported are 1 and 4. */
531 dimmInfo->burstLengthSupported = data[i];
533 DP(printf("Burst Length Supported: "));
534 if (dimmInfo->burstLengthSupported & 0x01)
536 if (dimmInfo->burstLengthSupported & 0x02)
538 if (dimmInfo->burstLengthSupported & 0x04)
540 if (dimmInfo->burstLengthSupported & 0x08)
542 DP(printf(" Bit \n"));
545 /*------------------------------------------------------------------------------------------------------------------------------*/
547 case 17: /* Number Of Banks On Each Device */
548 dimmInfo->numOfBanksOnEachDevice = data[i];
549 DP(printf("Number Of Banks On Each Chip: %d\n", dimmInfo->numOfBanksOnEachDevice));
551 /*------------------------------------------------------------------------------------------------------------------------------*/
553 case 18: /* Suported Cas Latencies */
556 *******-******-******-******-******-******-******-*******
557 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
558 *******-******-******-******-******-******-******-*******
559 CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
560 *********************************************************
562 *******-******-******-******-******-******-******-*******
563 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
564 *******-******-******-******-******-******-******-*******
565 CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 *
566 ********************************************************/
567 dimmInfo->suportedCasLatencies = data[i];
569 DP(printf("Suported Cas Latencies: (CL) "));
570 if (dimmInfo->memoryType == 0) /* SDRAM*/
572 for (k = 0; k <=7; k++)
574 if (dimmInfo->suportedCasLatencies & (1 << k))
575 DP(printf("%d, ", k+1));
581 if (dimmInfo->suportedCasLatencies & 1)
583 if (dimmInfo->suportedCasLatencies & 2)
585 if (dimmInfo->suportedCasLatencies & 4)
587 if (dimmInfo->suportedCasLatencies & 8)
589 if (dimmInfo->suportedCasLatencies & 16)
591 if (dimmInfo->suportedCasLatencies & 32)
597 /* Calculating MAX CAS latency */
598 for(j = 7 ; j > 0 ; j--)
600 if(((dimmInfo->suportedCasLatencies >> j) & 0x1) == 1)
602 switch(dimmInfo->memoryType)
605 /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
609 DP(printf("Max. Cas Latencies (DDR): ERROR !!!\n"));
610 dimmInfo->maxClSupported_DDR = DDR_CL_FAULT;
614 DP(printf("Max. Cas Latencies (DDR): ERROR !!!\n"));
615 dimmInfo->maxClSupported_DDR = DDR_CL_FAULT;
619 DP(printf("Max. Cas Latencies (DDR): 3.5 clk's\n"));
620 dimmInfo->maxClSupported_DDR = DDR_CL_3_5;
623 DP(printf("Max. Cas Latencies (DDR): 3 clk's \n"));
624 dimmInfo->maxClSupported_DDR = DDR_CL_3;
627 DP(printf("Max. Cas Latencies (DDR): 2.5 clk's \n"));
628 dimmInfo->maxClSupported_DDR = DDR_CL_2_5;
631 DP(printf("Max. Cas Latencies (DDR): 2 clk's \n"));
632 dimmInfo->maxClSupported_DDR = DDR_CL_2;
635 DP(printf("Max. Cas Latencies (DDR): 1.5 clk's \n"));
636 dimmInfo->maxClSupported_DDR = DDR_CL_1_5;
639 dimmInfo->maxCASlatencySupported_LoP = 1 + (int) (5 * j /10);
640 if (((5*j) % 10) != 0)
641 dimmInfo->maxCASlatencySupported_RoP = 5;
643 dimmInfo->maxCASlatencySupported_RoP = 0;
644 DP(printf("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo->maxCASlatencySupported_LoP, dimmInfo->maxCASlatencySupported_RoP));
647 /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
648 dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */
649 DP(printf("Max. Cas Latencies (SD): %d\n", dimmInfo->maxClSupported_SD));
650 dimmInfo->maxCASlatencySupported_LoP = j ;
651 dimmInfo->maxCASlatencySupported_RoP = 0;
652 DP(printf("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo->maxCASlatencySupported_LoP, dimmInfo->maxCASlatencySupported_RoP));
659 /*------------------------------------------------------------------------------------------------------------------------------*/
661 case 21: /* Buffered Address And Control Inputs */
662 DP(printf("\nModul Attributes (SPD Byte 21): \n"));
663 dimmInfo->bufferedAddrAndControlInputs = data[i] & BIT0;
664 dimmInfo->registeredAddrAndControlInputs = (data[i] & BIT1) >> 1;
665 dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
666 dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
667 dimmInfo->registeredDQMBinputs = (data[i] & BIT4) >> 4;
668 dimmInfo->differentialClockInput = (data[i] & BIT5) >> 5;
669 dimmInfo->redundantRowAddressing = (data[i] & BIT6) >> 6;
671 if (dimmInfo->bufferedAddrAndControlInputs == 1)
672 DP(printf(" - Buffered Address/Control Input: Yes \n"));
674 DP(printf(" - Buffered Address/Control Input: No \n"));
676 if (dimmInfo->registeredAddrAndControlInputs == 1)
677 DP(printf(" - Registered Address/Control Input: Yes \n"));
679 DP(printf(" - Registered Address/Control Input: No \n"));
681 if (dimmInfo->onCardPLL == 1)
682 DP(printf(" - On-Card PLL (clock): Yes \n"));
684 DP(printf(" - On-Card PLL (clock): No \n"));
686 if (dimmInfo->bufferedDQMBinputs == 1)
687 DP(printf(" - Bufferd DQMB Inputs: Yes \n"));
689 DP(printf(" - Bufferd DQMB Inputs: No \n"));
691 if (dimmInfo->registeredDQMBinputs == 1)
692 DP(printf(" - Registered DQMB Inputs: Yes \n"));
694 DP(printf(" - Registered DQMB Inputs: No \n"));
696 if (dimmInfo->differentialClockInput == 1)
697 DP(printf(" - Differential Clock Input: Yes \n"));
699 DP(printf(" - Differential Clock Input: No \n"));
701 if (dimmInfo->redundantRowAddressing == 1)
702 DP(printf(" - redundant Row Addressing: Yes \n"));
704 DP(printf(" - redundant Row Addressing: No \n"));
708 /*------------------------------------------------------------------------------------------------------------------------------*/
710 case 22: /* Suported AutoPreCharge */
711 DP(printf("\nModul Attributes (SPD Byte 22): \n"));
712 dimmInfo->suportedEarlyRasPreCharge= data[i] & BIT0;
713 dimmInfo->suportedAutoPreCharge = (data[i] & BIT1) >> 1;
714 dimmInfo->suportedPreChargeAll = (data[i] & BIT2) >> 2;
715 dimmInfo->suportedWrite1ReadBurst= (data[i] & BIT3) >> 3;
716 dimmInfo->suported5PercentLowVCC= (data[i] & BIT4) >> 4;
717 dimmInfo->suported5PercentUpperVCC= (data[i] & BIT5) >> 5;
719 if (dimmInfo->suportedEarlyRasPreCharge == 1)
720 DP(printf(" - Early Ras Precharge: Yes \n"));
722 DP(printf(" - Early Ras Precharge: No \n"));
724 if (dimmInfo->suportedAutoPreCharge == 1)
725 DP(printf(" - AutoPreCharge: Yes \n"));
727 DP(printf(" - AutoPreCharge: No \n"));
729 if (dimmInfo->suportedPreChargeAll == 1)
730 DP(printf(" - Precharge All: Yes \n"));
732 DP(printf(" - Precharge All: No \n"));
734 if (dimmInfo->suportedWrite1ReadBurst == 1)
735 DP(printf(" - Write 1/ReadBurst: Yes \n"));
737 DP(printf(" - Write 1/ReadBurst: No \n"));
739 if (dimmInfo->suported5PercentLowVCC == 1)
740 DP(printf(" - lower VCC tolerance: 5 Percent \n"));
742 DP(printf(" - lower VCC tolerance: 10 Percent \n"));
744 if (dimmInfo->suported5PercentUpperVCC == 1)
745 DP(printf(" - upper VCC tolerance: 5 Percent \n"));
747 DP(printf(" - upper VCC tolerance: 10 Percent \n"));
751 /*------------------------------------------------------------------------------------------------------------------------------*/
753 case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
754 shift = (dimmInfo->memoryType == DDR)? 4:2;
755 mult = (dimmInfo->memoryType == DDR)? 10:25;
756 maskLeftOfPoint = (dimmInfo->memoryType == DDR)? 0xf0:0xfc;
757 maskRightOfPoint = (dimmInfo->memoryType == DDR)? 0xf:0x03;
758 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
759 rightOfPoint = (data[i] & maskRightOfPoint)* mult;
760 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP = leftOfPoint;
761 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = rightOfPoint;
762 DP(printf("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",leftOfPoint, rightOfPoint ));
763 /*dimmInfo->minimumCycleTimeAtMaxCasLatancy*/
765 /*------------------------------------------------------------------------------------------------------------------------------*/
767 case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/
768 div = (dimmInfo->memoryType == DDR)? 100:10;
769 time_tmp = (((data[i] & 0xf0) >> 4)*10) + ((data[i] & 0x0f));
770 leftOfPoint = time_tmp / div;
771 rightOfPoint = time_tmp % div;
772 dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
773 dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
774 DP(printf("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",leftOfPoint, rightOfPoint ));
776 /*------------------------------------------------------------------------------------------------------------------------------*/
778 case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
779 shift = (dimmInfo->memoryType == DDR)? 4:2;
780 mult = (dimmInfo->memoryType == DDR)? 10:25;
781 maskLeftOfPoint = (dimmInfo->memoryType == DDR)? 0xf0:0xfc;
782 maskRightOfPoint = (dimmInfo->memoryType == DDR)? 0xf:0x03;
783 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
784 rightOfPoint = (data[i] & maskRightOfPoint)* mult;
785 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP = leftOfPoint;
786 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = rightOfPoint;
787 DP(printf("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",leftOfPoint, rightOfPoint ));
788 /*dimmInfo->minimumCycleTimeAtMaxCasLatancy*/
790 /*------------------------------------------------------------------------------------------------------------------------------*/
792 case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/
793 div = (dimmInfo->memoryType == DDR)? 100:10;
794 time_tmp = (((data[i] & 0xf0) >> 4)*10) + ((data[i] & 0x0f));
795 leftOfPoint = time_tmp / div;
796 rightOfPoint = time_tmp % div;
797 dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
798 dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
799 DP(printf("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",leftOfPoint, rightOfPoint ));
801 /*------------------------------------------------------------------------------------------------------------------------------*/
803 case 27: /* Minimum Row Precharge Time */
804 shift = (dimmInfo->memoryType == DDR)? 2:0;
805 maskLeftOfPoint = (dimmInfo->memoryType == DDR)? 0xfc:0xff;
806 maskRightOfPoint = (dimmInfo->memoryType == DDR)? 0x03:0x00;
807 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
808 rightOfPoint = (data[i] & maskRightOfPoint)*25;
810 dimmInfo->minRowPrechargeTime = ((leftOfPoint*100) + rightOfPoint); /* measured in n times 10ps Intervals */
811 trp_clocks = (dimmInfo->minRowPrechargeTime + (tmemclk-1)) / tmemclk;
812 DP(printf("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", tmemclk, tmemclk/100, tmemclk%100 ));
813 DP(printf("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", leftOfPoint, rightOfPoint, trp_clocks));
815 /*------------------------------------------------------------------------------------------------------------------------------*/
817 case 28: /* Minimum Row Active to Row Active Time */
818 shift = (dimmInfo->memoryType == DDR)? 2:0;
819 maskLeftOfPoint = (dimmInfo->memoryType == DDR)? 0xfc:0xff;
820 maskRightOfPoint = (dimmInfo->memoryType == DDR)? 0x03:0x00;
821 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
822 rightOfPoint = (data[i] & maskRightOfPoint)*25;
824 dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint*100) + rightOfPoint); /* measured in 100ns Intervals */
825 trrd_clocks = (dimmInfo->minRowActiveRowActiveDelay + (tmemclk-1)) / tmemclk;
826 DP(printf("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", leftOfPoint, rightOfPoint, trp_clocks));
828 /*------------------------------------------------------------------------------------------------------------------------------*/
830 case 29: /* Minimum Ras-To-Cas Delay */
831 shift = (dimmInfo->memoryType == DDR)? 2:0;
832 maskLeftOfPoint = (dimmInfo->memoryType == DDR)? 0xfc:0xff;
833 maskRightOfPoint = (dimmInfo->memoryType == DDR)? 0x03:0x00;
834 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
835 rightOfPoint = (data[i] & maskRightOfPoint)*25;
837 dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint*100) + rightOfPoint); /* measured in 100ns Intervals */
838 trcd_clocks = (dimmInfo->minRowActiveRowActiveDelay + (tmemclk-1) )/ tmemclk;
839 DP(printf("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", leftOfPoint, rightOfPoint, trp_clocks));
841 /*------------------------------------------------------------------------------------------------------------------------------*/
843 case 30: /* Minimum Ras Pulse Width */
844 dimmInfo->minRasPulseWidth = data[i];
845 tras_clocks = (NSto10PS(data[i])+(tmemclk-1)) / tmemclk;
846 DP(printf("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", dimmInfo->minRasPulseWidth, tras_clocks));
849 /*------------------------------------------------------------------------------------------------------------------------------*/
851 case 31: /* Module Bank Density */
852 dimmInfo->moduleBankDensity = data[i];
853 DP(printf("Module Bank Density: %d\n", dimmInfo->moduleBankDensity));
855 DP(printf("*** Offered Densities (more than 1 = Multisize-Module): "));
857 if (dimmInfo->moduleBankDensity & 1)
859 if (dimmInfo->moduleBankDensity & 2)
861 if (dimmInfo->moduleBankDensity & 4)
862 DP(printf("16MB, "));
863 if (dimmInfo->moduleBankDensity & 8)
864 DP(printf("32MB, "));
865 if (dimmInfo->moduleBankDensity & 16)
866 DP(printf("64MB, "));
867 if (dimmInfo->moduleBankDensity & 32)
868 DP(printf("128MB, "));
869 if ((dimmInfo->moduleBankDensity & 64) || (dimmInfo->moduleBankDensity & 128)) {
870 DP(printf("ERROR, "));
877 /*------------------------------------------------------------------------------------------------------------------------------*/
879 case 32: /* Address And Command Setup Time (measured in ns/1000) */
881 switch(dimmInfo->memoryType)
884 time_tmp = (((data[i] & 0xf0) >> 4)*10) + ((data[i] & 0x0f));
885 leftOfPoint = time_tmp / 100;
886 rightOfPoint = time_tmp % 100;
889 leftOfPoint = (data[i] & 0xf0) >> 4;
892 leftOfPoint = data[i] & 0x70 >> 4;
895 rightOfPoint = (data[i] & 0x0f);
898 dimmInfo->addrAndCommandSetupTime = (leftOfPoint*100 + rightOfPoint) * sign;
899 DP(printf("Address And Command Setup Time [ns]: %d.%d\n", sign*leftOfPoint, rightOfPoint));
901 /*------------------------------------------------------------------------------------------------------------------------------*/
903 case 33: /* Address And Command Hold Time */
905 switch(dimmInfo->memoryType)
908 time_tmp = (((data[i] & 0xf0) >> 4)*10) + ((data[i] & 0x0f));
909 leftOfPoint = time_tmp / 100;
910 rightOfPoint = time_tmp % 100;
913 leftOfPoint = (data[i] & 0xf0) >> 4;
916 leftOfPoint = data[i] & 0x70 >> 4;
919 rightOfPoint = (data[i] & 0x0f) ;
922 dimmInfo->addrAndCommandHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign;
923 DP(printf("Address And Command Hold Time [ns]: %d.%d\n", sign*leftOfPoint, rightOfPoint));
925 /*------------------------------------------------------------------------------------------------------------------------------*/
927 case 34: /* Data Input Setup Time */
929 switch(dimmInfo->memoryType)
932 time_tmp = (((data[i] & 0xf0) >> 4)*10) + ((data[i] & 0x0f));
933 leftOfPoint = time_tmp / 100;
934 rightOfPoint = time_tmp % 100;
937 leftOfPoint = (data[i] & 0xf0) >> 4;
940 leftOfPoint = data[i] & 0x70 >> 4;
943 rightOfPoint = (data[i] & 0x0f );
946 dimmInfo->dataInputSetupTime = (leftOfPoint *100 + rightOfPoint) * sign;
947 DP(printf("Data Input Setup Time [ns]: %d.%d\n", sign*leftOfPoint, rightOfPoint));
949 /*------------------------------------------------------------------------------------------------------------------------------*/
951 case 35: /* Data Input Hold Time */
953 switch(dimmInfo->memoryType)
956 time_tmp = (((data[i] & 0xf0) >> 4)*10) + ((data[i] & 0x0f));
957 leftOfPoint = time_tmp / 100;
958 rightOfPoint = time_tmp % 100;
961 leftOfPoint = (data[i] & 0xf0) >> 4;
964 leftOfPoint = data[i] & 0x70 >> 4;
967 rightOfPoint = (data[i] & 0x0f) ;
970 dimmInfo->dataInputHoldTime = (leftOfPoint *100 + rightOfPoint) * sign;
971 DP(printf("Data Input Hold Time [ns]: %d.%d\n\n", sign*leftOfPoint, rightOfPoint));
973 /*------------------------------------------------------------------------------------------------------------------------------*/
976 /* calculating the sdram density */
977 for(i = 0;i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;i++)
981 dimmInfo->deviceDensity = density*dimmInfo->numOfBanksOnEachDevice*
982 dimmInfo->sdramWidth;
983 dimmInfo->numberOfDevices = (dimmInfo->dataWidth / dimmInfo->sdramWidth)*
984 dimmInfo->numOfModuleBanks;
985 devicesForErrCheck = (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth ;
986 if((dimmInfo->errorCheckType == 0x1) ||
987 (dimmInfo->errorCheckType == 0x2) ||
988 (dimmInfo->errorCheckType == 0x3))
990 dimmInfo->size = (dimmInfo->deviceDensity / 8)*
991 (dimmInfo->numberOfDevices - devicesForErrCheck);
995 dimmInfo->size = (dimmInfo->deviceDensity/8)*dimmInfo->numberOfDevices;
998 /* compute the module DRB size */
999 tmp = (1 << (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
1000 tmp *= dimmInfo->numOfModuleBanks;
1001 tmp *= dimmInfo->sdramWidth;
1002 tmp = tmp >> 24; /* div by 0x4000000 (64M) */
1003 dimmInfo->drb_size = (uchar)tmp;
1004 DP(printf("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
1006 /* try a CAS latency of 3 first... */
1008 /* bit 1 is CL2, bit 2 is CL3 */
1009 supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
1013 if (NS10to10PS(data[9]) <= tmemclk)
1017 if (NS10to10PS(data[9]) <= tmemclk)
1023 if (NS10to10PS(data[23]) <= tmemclk)
1027 DP(printf("cal_val = %d\n", cal_val*5));
1029 /* bummer, did't work... */
1031 DP(printf("Couldn't find a good CAS latency\n"));
1039 /* sets up the GT properly with information passed in */
1041 setup_sdram(AUX_MEM_DIMM_INFO *info)
1044 ulong tmp_sdram_mode=0; /* 0x141c*/
1045 ulong tmp_dunit_control_low=0; /* 0x1404*/
1048 /* sanity checking */
1049 if (! info->numOfModuleBanks) {
1050 printf("setup_sdram called with 0 banks\n");
1056 /* Program the GT with the discovered data */
1057 if (info->registeredAddrAndControlInputs == true)
1058 DP(printf("Module is registered, but we do not support registered Modules !!!\n"));
1062 set_dfcdlInit(); /* may be its not needed */
1063 DP(printf("Delay line set done\n"));
1065 /* set SDRAM mode NOP*/ /* To_do check it*/
1066 GT_REG_WRITE(SDRAM_OPERATION, 0x5);
1067 while (GTREGREAD(SDRAM_OPERATION) != 0) {
1068 DP(printf("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
1071 /* SDRAM configuration */
1072 GT_REG_WRITE(SDRAM_CONFIG, 0x58200400);
1073 DP(printf("sdram_conf 0x1400: %08x\n", GTREGREAD(SDRAM_CONFIG)));
1075 /* SDRAM open pages controll keep open as much as I can*/
1076 GT_REG_WRITE(SDRAM_OPEN_PAGES_CONTROL, 0x0);
1077 DP(printf("sdram_open_pages_controll 0x1414: %08x\n", GTREGREAD(SDRAM_OPEN_PAGES_CONTROL)));
1080 /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1081 tmp = (GTREGREAD(D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset*/
1083 DP(printf("Core Signals are sync (by HW-Setting)!!!\n"));
1085 DP(printf("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
1087 /* SDRAM set CAS Lentency according to SPD information*/
1088 switch(info->memoryType)
1091 DP(printf("### SD-RAM not supported yet !!!\n"));
1093 /* ToDo fill SD-RAM if needed !!!!!*/
1097 DP(printf("### SET-CL for DDR-RAM\n"));
1099 switch (info->maxClSupported_DDR)
1102 tmp_dunit_control_low = 0x3c000000; /* Read-Data sampled on falling edge of Clk*/
1103 tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4*/
1104 DP(printf("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
1108 if (tmp == 1) /* clocks sync*/
1110 tmp_dunit_control_low = 0x24000000; /* Read-Data sampled on falling edge of Clk*/
1111 tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4*/
1112 DP(printf("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
1114 else /* clk sync. bypassed */
1116 tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk*/
1117 tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4*/
1118 DP(printf("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
1123 if (tmp == 1) /* Sync*/
1125 tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk*/
1126 tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4*/
1127 DP(printf("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
1129 else /* Not sync. */
1131 tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk*/
1132 tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4*/
1133 DP(printf("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
1138 if (tmp == 1) /* Sync*/
1140 tmp_dunit_control_low = 0x23000000; /* Read-Data sampled on falling edge of Clk*/
1141 tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4*/
1142 DP(printf("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
1146 tmp_dunit_control_low = 0x1a000000; /* Read-Data sampled on rising edge of Clk*/
1147 tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4*/
1148 DP(printf("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
1153 printf("Max. CL is out of range %d\n", info->maxClSupported_DDR);
1160 /* Write results of CL detection procedure */
1161 GT_REG_WRITE(SDRAM_MODE, tmp_sdram_mode);
1162 /* set SDRAM mode SetCommand 0x1418*/
1163 GT_REG_WRITE(SDRAM_OPERATION, 0x3);
1164 while (GTREGREAD(SDRAM_OPERATION) != 0) {
1165 DP(printf("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1169 /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1170 tmp = (GTREGREAD(D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset*/
1171 if (tmp != 1) /*clocks are not sync*/
1174 GT_REG_WRITE(D_UNIT_CONTROL_LOW ,
1175 (GTREGREAD(D_UNIT_CONTROL_LOW) & 0x7F) | 0x18110780 | tmp_dunit_control_low );
1180 GT_REG_WRITE(D_UNIT_CONTROL_LOW ,
1181 (GTREGREAD(D_UNIT_CONTROL_LOW) & 0x7F) | 0x00110000 | tmp_dunit_control_low );
1184 /* set SDRAM mode SetCommand 0x1418*/
1185 GT_REG_WRITE(SDRAM_OPERATION, 0x3);
1186 while (GTREGREAD(SDRAM_OPERATION) != 0) {
1187 DP(printf("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
1190 /*------------------------------------------------------------------------------ */
1193 /* bank parameters */
1194 /* SDRAM address decode register */
1195 /* program this with the default value */
1199 DP(printf("drb_size (n*64Mbit): %d\n", info->drb_size));
1200 switch (info->drb_size) {
1201 case 1: /* 64 Mbit */
1202 case 2: /* 128 Mbit */
1203 DP(printf("RAM-Device_size 64Mbit or 128Mbit)\n"));
1206 case 4: /* 256 Mbit */
1207 case 8: /* 512 Mbit */
1208 DP(printf("RAM-Device_size 256Mbit or 512Mbit)\n"));
1211 case 16: /* 1 Gbit */
1212 case 32: /* 2 Gbit */
1213 DP(printf("RAM-Device_size 1Gbit or 2Gbit)\n"));
1217 printf("Error in dram size calculation\n");
1218 DP(printf("Assume: RAM-Device_size 1Gbit or 2Gbit)\n"));
1223 /* SDRAM bank parameters */
1224 /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
1225 DP(printf("setting up slot %d config with: %08lx \n", info->slot, tmp));
1226 GT_REG_WRITE(SDRAM_ADDR_CONTROL, tmp);
1228 /* ------------------------------------------------------------------------------ */
1230 DP(printf("setting up sdram_timing_control_low with: %08x \n", 0x11511220));
1231 GT_REG_WRITE(SDRAM_TIMING_CONTROL_LOW, 0x11511220);
1234 /* ------------------------------------------------------------------------------ */
1236 /* SDRAM configuration */
1237 tmp = GTREGREAD(SDRAM_CONFIG);
1239 if (info->registeredAddrAndControlInputs || info->registeredDQMBinputs) {
1241 DP(printf("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",info->registeredAddrAndControlInputs, info->registeredDQMBinputs));
1244 /* Use buffer 1 to return read data to the CPU
1245 * Page 426 MV64360 */
1247 DP(printf("Before Buffer assignment - sdram_conf: %08x\n", GTREGREAD(SDRAM_CONFIG)));
1248 DP(printf("After Buffer assignment - sdram_conf: %08x\n", GTREGREAD(SDRAM_CONFIG)));
1250 /* SDRAM timing To_do:*/
1253 tmp = GTREGREAD(SDRAM_TIMING_CONTROL_HIGH);
1254 DP(printf("# sdram_timing_control_high is : %08lx \n", tmp));
1256 /* SDRAM address decode register */
1257 /* program this with the default value */
1258 tmp = GTREGREAD(SDRAM_ADDR_CONTROL);
1259 DP(printf("SDRAM address control (before: decode): %08x ", GTREGREAD(SDRAM_ADDR_CONTROL)));
1260 GT_REG_WRITE(SDRAM_ADDR_CONTROL, (tmp | 0x2));
1261 DP(printf("SDRAM address control (after: decode): %08x\n", GTREGREAD(SDRAM_ADDR_CONTROL)));
1263 /* set the SDRAM configuration for each bank */
1265 /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
1268 DP(printf("\n*** Running a MRS cycle for bank %d ***\n", i));
1271 memory_map_bank(i, 0, GB/4);
1272 #if 1 /* test only */
1273 /* set SDRAM mode */ /* To_do check it*/
1274 GT_REG_WRITE(SDRAM_OPERATION, 0x3);
1275 check = GTREGREAD(SDRAM_OPERATION);
1276 DP(printf("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", check));
1279 /* switch back to normal operation mode */
1280 GT_REG_WRITE(SDRAM_OPERATION, 0);
1281 check = GTREGREAD(SDRAM_OPERATION);
1282 DP(printf("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", check));
1283 #endif /* test only */
1284 /* unmap the bank */
1285 memory_map_bank(i, 0, 0);
1292 * Check memory range for valid RAM. A simple memory test determines
1293 * the actually available RAM size between addresses `base' and
1294 * `base + maxsize'. Some (not all) hardware errors are detected:
1295 * - short between address lines
1296 * - short between data lines
1299 dram_size(long int *base, long int maxsize)
1301 volatile long int *addr, *b=base;
1302 long int cnt, val, save1, save2;
1304 #define STARTVAL (1<<20) /* start test at 1M */
1305 for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
1306 addr = base + cnt; /* pointer arith! */
1308 save1=*addr; /* save contents of addr */
1309 save2=*b; /* save contents of base */
1311 *addr=cnt; /* write cnt to addr */
1312 *b=0; /* put null at base */
1314 /* check at base address */
1316 *addr=save1; /* restore *addr */
1317 *b=save2; /* restore *b */
1320 val = *addr; /* read *addr */
1321 val = *addr; /* read *addr */
1327 DP(printf("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr));
1328 /* fix boundary condition.. STARTVAL means zero */
1329 if(cnt==STARTVAL/sizeof(long)) cnt=0;
1330 return (cnt * sizeof(long));
1336 /* ------------------------------------------------------------------------- */
1338 /* ppcboot interface function to SDRAM init - this is where all the
1339 * controlling logic happens */
1341 initdram(int board_type)
1344 int checkbank[4] = { [0 ... 3] = 0 };
1345 ulong bank_no, realsize, total, check;
1346 AUX_MEM_DIMM_INFO dimmInfo1;
1347 AUX_MEM_DIMM_INFO dimmInfo2;
1350 /* first, use the SPD to get info about the SDRAM/ DDRRAM */
1352 /* check the NHR bit and skip mem init if it's already done */
1353 nhr = get_hid0() & (1 << 16);
1356 printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
1359 s0 = check_dimm(0, &dimmInfo1);
1362 s1 = check_dimm(1, &dimmInfo2);
1364 memory_map_bank(0, 0, 0);
1365 memory_map_bank(1, 0, 0);
1366 memory_map_bank(2, 0, 0);
1367 memory_map_bank(3, 0, 0);
1369 if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) {
1370 printf("Setup for DIMM1 failed.\n");
1373 if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) {
1374 printf("Setup for DIMM2 failed.\n");
1377 /* set the NHR bit */
1378 set_hid0(get_hid0() | (1 << 16));
1380 /* next, size the SDRAM banks */
1382 realsize = total = 0;
1384 if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");}
1385 if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");}
1386 if (dimmInfo1.numOfModuleBanks > 2)
1387 printf("Error, SPD claims DIMM1 has >2 banks\n");
1389 if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");}
1390 if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");}
1391 if (dimmInfo2.numOfModuleBanks > 2)
1392 printf("Error, SPD claims DIMM2 has >2 banks\n");
1394 for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
1395 /* skip over banks that are not populated */
1396 if (! checkbank[bank_no])
1399 if ((total + check) > CFG_GT_REGS)
1400 check = CFG_GT_REGS - total;
1402 memory_map_bank(bank_no, total, check);
1403 realsize = dram_size((long int *)total, check);
1404 memory_map_bank(bank_no, total, realsize);
1409 /* Setup Ethernet DMA Adress window to DRAM Area */
1413 /* ***************************************************************************************
1415 ! * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb *
1416 ! * This procedure fits only the Atlantis *
1418 ! *************************************************************************************** */
1421 /* ***************************************************************************************
1422 ! * DFCDL initialize MV643xx Design Considerations *
1424 ! *************************************************************************************** */
1429 unsigned int dfcdl_word = 0x0000014f;
1430 for (i=0 ; i < 64; i++)
1432 GT_REG_WRITE(SRAM_DATA0, dfcdl_word);
1434 GT_REG_WRITE(DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */