3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
24 * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
28 * cpci750.c - main board support/init for the esd cpci750.
34 #include "../../Marvell/include/memory.h"
35 #include "../../Marvell/include/pci.h"
36 #include "../../Marvell/include/mv_gen_reg.h"
50 #endif /* of CONFIG_PCI */
58 static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */
59 {"PCI0DLL_1 "}, /* 30 */
60 {"PCI0DLL_0 "}, /* 29 */
61 {"PCI1DLL_2 "}, /* 28 */
62 {"PCI1DLL_1 "}, /* 27 */
63 {"PCI1DLL_0 "}, /* 26 */
64 {"BbEP2En "}, /* 25 */
65 {"SDRAMRdDataDel"}, /* 24 */
66 {"SDRAMRdDel "}, /* 23 */
67 {"SDRAMSync "}, /* 22 */
68 {"SDRAMPipeSel_1"}, /* 21 */
69 {"SDRAMPipeSel_0"}, /* 20 */
70 {"SDRAMAddDel "}, /* 19 */
71 {"SDRAMClkSel "}, /* 18 */
72 {"Reserved(1!) "}, /* 17 */
74 {"BootCSWidth_1 "}, /* 15 */
75 {"BootCSWidth_0 "}, /* 14 */
76 {"PCI1PadsCal "}, /* 13 */
77 {"PCI0PadsCal "}, /* 12 */
78 {"MultiMVId_1 "}, /* 11 */
79 {"MultiMVId_0 "}, /* 10 */
80 {"MultiGTEn "}, /* 09 */
81 {"Int60xArb "}, /* 08 */
82 {"CPUBusConfig_1"}, /* 07 */
83 {"CPUBusConfig_0"}, /* 06 */
84 {"DefIntSpc "}, /* 05 */
86 {"SROMAdd_1 "}, /* 03 */
87 {"SROMAdd_0 "}, /* 02 */
88 {"DRAMPadCal "}, /* 01 */
89 {"SInitEn "}, /* 00 */
100 {"JTAGCalBy "}, /* 21 */
101 {"GB2Sel "}, /* 20 */
102 {"GB1Sel "}, /* 19 */
103 {"DRAMPLL_MDiv_5"}, /* 18 */
104 {"DRAMPLL_MDiv_4"}, /* 17 */
105 {"DRAMPLL_MDiv_3"}, /* 16 */
106 {"DRAMPLL_MDiv_2"}, /* 15 */
107 {"DRAMPLL_MDiv_1"}, /* 14 */
108 {"DRAMPLL_MDiv_0"}, /* 13 */
109 {"GB0Sel "}, /* 12 */
110 {"DRAMPLLPU "}, /* 11 */
111 {"DRAMPLL_HIKVCO"}, /* 10 */
112 {"DRAMPLLNP "}, /* 09 */
113 {"DRAMPLL_NDiv_7"}, /* 08 */
114 {"DRAMPLL_NDiv_6"}, /* 07 */
115 {"CPUPadCal "}, /* 06 */
116 {"DRAMPLL_NDiv_5"}, /* 05 */
117 {"DRAMPLL_NDiv_4"}, /* 04 */
118 {"DRAMPLL_NDiv_3"}, /* 03 */
119 {"DRAMPLL_NDiv_2"}, /* 02 */
120 {"DRAMPLL_NDiv_1"}, /* 01 */
121 {"DRAMPLL_NDiv_0"}}; /* 00 */
123 extern flash_info_t flash_info[];
125 extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
126 extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
128 /* ------------------------------------------------------------------------- */
130 /* this is the current GT register space location */
131 /* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
133 /* Unfortunately, we cant change it while we are in flash, so we initialize it
134 * to the "final" value. This means that any debug_led calls before
135 * board_early_init_f wont work right (like in cpu_init_f).
136 * See also my_remap_gt_regs below. (NTL)
139 void board_prebootm_init (void);
140 unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
141 int display_mem_map (void);
143 /* ------------------------------------------------------------------------- */
146 * This is a version of the GT register space remapping function that
147 * doesn't touch globals (meaning, it's ok to run from flash.)
149 * Unfortunately, this has the side effect that a writable
150 * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
153 void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
157 /* check and see if it's already moved */
159 /* original ppcboot 1.1.6 source
161 temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
162 if ((temp & 0xffff) == new_loc >> 20)
165 temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
166 0xffff0000) | (new_loc >> 20);
168 out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
170 while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
171 original ppcboot 1.1.6 source end */
173 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
174 if ((temp & 0xffff) == new_loc >> 16)
177 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
178 0xffff0000) | (new_loc >> 16);
180 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
182 while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
187 static void gt_pci_config (void)
191 unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
193 /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
194 * config registers by writing ones to the bus and device.
195 * We then update the Virtual register with the correct value for the bus and device.
197 if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
198 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
200 GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
202 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
203 GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
204 (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
207 if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
208 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
209 GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
211 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
212 GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
213 (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
217 PCI_MASTER_ENABLE (0, SELF);
218 PCI_MASTER_ENABLE (1, SELF);
220 /* Enable PCI0/1 Mem0 and IO 0 disable all others */
221 GT_REG_READ (BASE_ADDR_ENABLE, &stat);
222 stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
225 stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
226 GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
228 /* ronen- add write to pci remap registers for 64460.
229 in 64360 when writing to pci base go and overide remap automaticaly,
230 in 64460 it doesn't */
231 GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
232 GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
233 GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
235 GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
236 GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
237 GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
239 GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
240 GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
241 GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
243 GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
244 GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
245 GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
247 /* PCI interface settings */
248 /* Timeout set to retry forever */
249 GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
250 GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
252 /* ronen - enable only CS0 and Internal reg!! */
253 GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
254 GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
256 /*ronen update the pci internal registers base address.*/
258 for (stat = 0; stat <= PCI_HOST1; stat++) {
259 data = pciReadConfigReg(stat,
260 PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
262 data = (data & 0x0f) | CONFIG_SYS_GT_REGS;
263 pciWriteConfigReg (stat,
264 PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
272 /* Setup CPU interface paramaters */
273 static void gt_cpu_config (void)
275 cpu_t cpu = get_cpu_type ();
278 /* cpu configuration register */
279 tmp = GTREGREAD (CPU_CONFIGURATION);
281 /* set the SINGLE_CPU bit see MV64360 P.399 */
282 #ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
283 tmp |= CPU_CONF_SINGLE_CPU;
286 tmp &= ~CPU_CONF_AACK_DELAY_2;
288 tmp |= CPU_CONF_DP_VALID;
289 tmp |= CPU_CONF_AP_VALID;
291 tmp |= CPU_CONF_PIPELINE;
293 GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
295 /* CPU master control register */
296 tmp = GTREGREAD (CPU_MASTER_CONTROL);
298 tmp |= CPU_MAST_CTL_ARB_EN;
300 if ((cpu == CPU_7400) ||
301 (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
303 tmp |= CPU_MAST_CTL_CLEAN_BLK;
304 tmp |= CPU_MAST_CTL_FLUSH_BLK;
307 /* cleanblock must be cleared for CPUs
308 * that do not support this command (603e, 750)
310 tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
311 tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
313 GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
317 * board_early_init_f.
319 * set up gal. device mappings, etc.
321 int board_early_init_f (void)
325 * set up the GT the way the kernel wants it
326 * the call to move the GT register space will obviously
327 * fail if it has already been done, but we're going to assume
328 * that if it's not at the power-on location, it's where we put
329 * it last time. (huber)
332 my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
334 /* No PCI in first release of Port To_do: enable it. */
338 /* mask all external interrupt sources */
339 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
340 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
342 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
343 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
344 /* --------------------- */
345 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
346 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
347 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
348 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
349 /* does not exist in MV6436x
350 GT_REG_WRITE(CPU_INT_0_MASK, 0);
351 GT_REG_WRITE(CPU_INT_1_MASK, 0);
352 GT_REG_WRITE(CPU_INT_2_MASK, 0);
353 GT_REG_WRITE(CPU_INT_3_MASK, 0);
354 --------------------- */
357 /* ----- DEVICE BUS SETTINGS ------ */
364 * 3 - Flash checked 32Bit Intel Strata
365 * boot - BootCS checked 8Bit 29LV040B
370 * the dual 7450 module requires burst access to the boot
371 * device, so the serial rom copies the boot device to the
372 * on-board sram on the eval board, and updates the correct
373 * registers to boot from the sram. (device0)
376 memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
377 memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
378 memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
379 memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
382 /* configure device timing */
383 GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
384 GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
385 GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
386 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR);
388 #ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
389 /* detect if we are booting from the 32 bit flash */
390 if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
391 /* 32 bit boot flash */
392 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
393 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
394 CONFIG_SYS_32BIT_BOOT_PAR);
396 /* 8 bit boot flash */
397 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
398 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
401 /* 8 bit boot flash only */
402 /* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
409 GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
410 GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
411 GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
412 GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
414 GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
422 /* various things to do after relocation */
437 /* disable the dcache and MMU */
440 if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) {
441 unsigned int flash_offset;
444 flash_offset = CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size;
445 for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) {
446 if (flash_info[3].start[l] != 0) {
447 flash_info[3].start[l] += flash_offset;
450 flash_protect (FLAG_PROTECT_SET,
451 CONFIG_SYS_MONITOR_BASE,
452 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
458 void after_reloc (ulong dest_addr, gd_t * gd)
460 memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE,
461 CONFIG_SYS_BOOT_SIZE);
464 GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
465 GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
467 /* now, jump to the main ppcboot board init code */
468 board_init_r (gd, dest_addr);
472 /* ------------------------------------------------------------------------- */
475 * Check Board Identity:
477 * right now, assume borad type. (there is just one...after all)
480 int checkboard (void)
484 printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
488 /* utility functions */
489 void debug_led (int led, int mode)
493 int display_mem_map (void)
496 unsigned int base, size, width;
499 printf ("SD (DDR) RAM\n");
500 for (i = 0; i <= BANK3; i++) {
501 base = memoryGetBankBaseAddress (i);
502 size = memoryGetBankSize (i);
504 printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
505 i, base, size >> 20);
509 /* CPU's PCI windows */
510 for (i = 0; i <= PCI_HOST1; i++) {
511 printf ("\nCPU's PCI %d windows\n", i);
512 base = pciGetSpaceBase (i, PCI_IO);
513 size = pciGetSpaceSize (i, PCI_IO);
514 printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
519 /*ronen currently only first PCI MEM is used 3 */ ;
521 base = pciGetSpaceBase (i, j);
522 size = pciGetSpaceSize (i, j);
523 printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
526 #endif /* of CONFIG_PCI */
528 printf ("\nDEVICES\n");
529 for (i = 0; i <= DEVICE3; i++) {
530 base = memoryGetDeviceBaseAddress (i);
531 size = memoryGetDeviceSize (i);
532 width = memoryGetDeviceWidth (i) * 8;
533 printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
535 printf ("\t- FLASH\n");
537 printf ("\t- FLASH\n");
539 printf ("\t- FLASH\n");
541 printf ("\t- RTC/REGS/CAN\n");
545 base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
546 size = memoryGetDeviceSize (BOOT_DEVICE);
547 width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
548 printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n",
549 base, size >> 20, width);
554 * Command loadpci: wait for signal from host and boot image.
556 int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
558 volatile unsigned int *ptr;
563 char str[] = "\\|/-";
572 puts("\nWaiting for image from pci host -");
575 * Wait for host to write the start address
577 while (*ptr == 0xffffffff) {
579 if (!(count % 100)) {
581 putc(0x08); /* backspace */
582 putc(str[count2 % 4]);
585 /* Abort if ctrl-c was pressed */
594 sprintf(addr, "%08x", *ptr);
595 printf("\nBooting Image at addr 0x%s ...\n", addr);
596 setenv("loadaddr", addr);
598 switch (ptr[1] == 0) {
601 * Boot image via bootm
603 local_args[0] = argv[0];
604 local_args[1] = NULL;
605 status = do_bootm (cmdtp, 0, 1, local_args);
609 * Boot image via bootvx
611 local_args[0] = argv[0];
612 local_args[1] = NULL;
613 status = do_bootvx (cmdtp, 0, 1, local_args);
621 loadpci, 1, 1, do_loadpci,
622 "loadpci - Wait for pci-image and boot it\n",
626 /* DRAM check routines copied from gw8260 */
628 #if defined (CONFIG_SYS_DRAM_TEST)
630 /*********************************************************************/
631 /* NAME: move64() - moves a double word (64-bit) */
634 /* this function performs a double word move from the data at */
635 /* the source pointer to the location at the destination pointer. */
638 /* unsigned long long *src - pointer to data to move */
641 /* unsigned long long *dest - pointer to locate to move data */
646 /* RESTRICTIONS/LIMITATIONS: */
647 /* May cloober fr0. */
649 /*********************************************************************/
650 static void move64 (unsigned long long *src, unsigned long long *dest)
652 asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
653 "stfd 0, 0(4)" /* *dest = fpr0 */
654 : : : "fr0"); /* Clobbers fr0 */
659 #if defined (CONFIG_SYS_DRAM_TEST_DATA)
661 unsigned long long pattern[] = {
662 0xaaaaaaaaaaaaaaaaLL,
663 0xccccccccccccccccLL,
664 0xf0f0f0f0f0f0f0f0LL,
665 0xff00ff00ff00ff00LL,
666 0xffff0000ffff0000LL,
667 0xffffffff00000000LL,
668 0x00000000ffffffffLL,
669 0x0000ffff0000ffffLL,
670 0x00ff00ff00ff00ffLL,
671 0x0f0f0f0f0f0f0f0fLL,
672 0x3333333333333333LL,
673 0x5555555555555555LL,
676 /*********************************************************************/
677 /* NAME: mem_test_data() - test data lines for shorts and opens */
680 /* Tests data lines for shorts and opens by forcing adjacent data */
681 /* to opposite states. Because the data lines could be routed in */
682 /* an arbitrary manner the must ensure test patterns ensure that */
683 /* every case is tested. By using the following series of binary */
684 /* patterns every combination of adjacent bits is test regardless */
687 /* ...101010101010101010101010 */
688 /* ...110011001100110011001100 */
689 /* ...111100001111000011110000 */
690 /* ...111111110000000011111111 */
692 /* Carrying this out, gives us six hex patterns as follows: */
694 /* 0xaaaaaaaaaaaaaaaa */
695 /* 0xcccccccccccccccc */
696 /* 0xf0f0f0f0f0f0f0f0 */
697 /* 0xff00ff00ff00ff00 */
698 /* 0xffff0000ffff0000 */
699 /* 0xffffffff00000000 */
701 /* The number test patterns will always be given by: */
703 /* log(base 2)(number data bits) = log2 (64) = 6 */
705 /* To test for short and opens to other signals on our boards. we */
707 /* test with the 1's complemnt of the paterns as well. */
710 /* Displays failing test pattern */
713 /* 0 - Passed test */
714 /* 1 - Failed test */
716 /* RESTRICTIONS/LIMITATIONS: */
717 /* Assumes only one one SDRAM bank */
719 /*********************************************************************/
720 int mem_test_data (void)
722 unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
723 unsigned long long temp64 = 0;
724 int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
728 for (i = 0; i < num_patterns; i++) {
729 move64 (&(pattern[i]), pmem);
730 move64 (pmem, &temp64);
732 /* hi = (temp64>>32) & 0xffffffff; */
733 /* lo = temp64 & 0xffffffff; */
734 /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
736 hi = (pattern[i] >> 32) & 0xffffffff;
737 lo = pattern[i] & 0xffffffff;
738 /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
740 if (temp64 != pattern[i]) {
741 printf ("\n Data Test Failed, pattern 0x%08x%08x",
749 #endif /* CONFIG_SYS_DRAM_TEST_DATA */
751 #if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
752 /*********************************************************************/
753 /* NAME: mem_test_address() - test address lines */
756 /* This function performs a test to verify that each word im */
757 /* memory is uniquly addressable. The test sequence is as follows: */
759 /* 1) write the address of each word to each word. */
760 /* 2) verify that each location equals its address */
763 /* Displays failing test pattern and address */
766 /* 0 - Passed test */
767 /* 1 - Failed test */
769 /* RESTRICTIONS/LIMITATIONS: */
772 /*********************************************************************/
773 int mem_test_address (void)
775 volatile unsigned int *pmem =
776 (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
777 const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
780 /* write address to each location */
781 for (i = 0; i < size; i++) {
785 /* verify each loaction */
786 for (i = 0; i < size; i++) {
788 printf ("\n Address Test Failed at 0x%x", i);
794 #endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
796 #if defined (CONFIG_SYS_DRAM_TEST_WALK)
797 /*********************************************************************/
798 /* NAME: mem_march() - memory march */
801 /* Marches up through memory. At each location verifies rmask if */
802 /* read = 1. At each location write wmask if write = 1. Displays */
803 /* failing address and pattern. */
806 /* volatile unsigned long long * base - start address of test */
807 /* unsigned int size - number of dwords(64-bit) to test */
808 /* unsigned long long rmask - read verify mask */
809 /* unsigned long long wmask - wrtie verify mask */
810 /* short read - verifies rmask if read = 1 */
811 /* short write - writes wmask if write = 1 */
814 /* Displays failing test pattern and address */
817 /* 0 - Passed test */
818 /* 1 - Failed test */
820 /* RESTRICTIONS/LIMITATIONS: */
823 /*********************************************************************/
824 int mem_march (volatile unsigned long long *base,
826 unsigned long long rmask,
827 unsigned long long wmask, short read, short write)
830 unsigned long long temp = 0;
831 unsigned int hitemp, lotemp, himask, lomask;
833 for (i = 0; i < size; i++) {
835 /* temp = base[i]; */
836 move64 ((unsigned long long *) &(base[i]), &temp);
838 hitemp = (temp >> 32) & 0xffffffff;
839 lotemp = temp & 0xffffffff;
840 himask = (rmask >> 32) & 0xffffffff;
841 lomask = rmask & 0xffffffff;
843 printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
848 /* base[i] = wmask; */
849 move64 (&wmask, (unsigned long long *) &(base[i]));
854 #endif /* CONFIG_SYS_DRAM_TEST_WALK */
856 /*********************************************************************/
857 /* NAME: mem_test_walk() - a simple walking ones test */
860 /* Performs a walking ones through entire physical memory. The */
861 /* test uses as series of memory marches, mem_march(), to verify */
862 /* and write the test patterns to memory. The test sequence is as */
864 /* 1) march writing 0000...0001 */
865 /* 2) march verifying 0000...0001 , writing 0000...0010 */
866 /* 3) repeat step 2 shifting masks left 1 bit each time unitl */
867 /* the write mask equals 1000...0000 */
868 /* 4) march verifying 1000...0000 */
869 /* The test fails if any of the memory marches return a failure. */
872 /* Displays which pass on the memory test is executing */
875 /* 0 - Passed test */
876 /* 1 - Failed test */
878 /* RESTRICTIONS/LIMITATIONS: */
881 /*********************************************************************/
882 int mem_test_walk (void)
884 unsigned long long mask;
885 volatile unsigned long long *pmem =
886 (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
887 const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
893 printf ("Initial Pass");
894 mem_march (pmem, size, 0x0, 0x1, 0, 1);
896 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
899 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
901 for (i = 0; i < 63; i++) {
902 printf ("Pass %2d", i + 2);
903 if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
904 /*printf("mask: 0x%x, pass: %d, ", mask, i); */
908 printf ("\b\b\b\b\b\b\b");
911 printf ("Last Pass");
912 if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
913 /* printf("mask: 0x%x", mask); */
916 printf ("\b\b\b\b\b\b\b\b\b");
918 printf ("\b\b\b\b\b\b\b\b\b");
923 /*********************************************************************/
924 /* NAME: testdram() - calls any enabled memory tests */
927 /* Runs memory tests if the environment test variables are set to */
931 /* testdramdata - If set to 'y', data test is run. */
932 /* testdramaddress - If set to 'y', address test is run. */
933 /* testdramwalk - If set to 'y', walking ones test is run */
939 /* 0 - Passed test */
940 /* 1 - Failed test */
942 /* RESTRICTIONS/LIMITATIONS: */
945 /*********************************************************************/
953 #ifdef CONFIG_SYS_DRAM_TEST_DATA
954 s = getenv ("testdramdata");
955 rundata = (s && (*s == 'y')) ? 1 : 0;
957 #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
958 s = getenv ("testdramaddress");
959 runaddress = (s && (*s == 'y')) ? 1 : 0;
961 #ifdef CONFIG_SYS_DRAM_TEST_WALK
962 s = getenv ("testdramwalk");
963 runwalk = (s && (*s == 'y')) ? 1 : 0;
966 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
967 printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
969 #ifdef CONFIG_SYS_DRAM_TEST_DATA
971 printf ("Test DATA ... ");
972 if (mem_test_data () == 1) {
973 printf ("failed \n");
979 #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
980 if (runaddress == 1) {
981 printf ("Test ADDRESS ... ");
982 if (mem_test_address () == 1) {
983 printf ("failed \n");
989 #ifdef CONFIG_SYS_DRAM_TEST_WALK
991 printf ("Test WALKING ONEs ... ");
992 if (mem_test_walk () == 1) {
993 printf ("failed \n");
999 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
1000 printf ("passed\n");
1005 #endif /* CONFIG_SYS_DRAM_TEST */
1007 /* ronen - the below functions are used by the bootm function */
1008 /* - we map the base register to fbe00000 (same mapping as in the LSP) */
1009 /* - we turn off the RX gig dmas - to prevent the dma from overunning */
1010 /* the kernel data areas. */
1011 /* - we diable and invalidate the icache and dcache. */
1012 void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
1016 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
1017 if ((temp & 0xffff) == new_loc >> 16)
1020 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
1021 0xffff0000) | (new_loc >> 16);
1023 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
1025 while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
1027 (INTERNAL_SPACE_DECODE)))))
1032 void board_prebootm_init ()
1035 /* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
1036 GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
1038 /* Stop GigE Rx DMA engines */
1039 GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
1040 /* GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */
1041 /* GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
1043 /* Relocate MV64360 internal regs */
1044 my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS);
1050 int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1052 unsigned int reset_sample_low;
1053 unsigned int reset_sample_high;
1054 unsigned int l, l1, l2;
1056 GT_REG_READ(0x3c4, &reset_sample_low);
1057 GT_REG_READ(0x3d4, &reset_sample_high);
1058 printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
1061 for (l=0; l<63; l++) {
1062 if (show_config_tab[l][0] != 0) {
1063 printf("%14s:%1x ", show_config_tab[l],
1064 ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
1072 reset_sample_low = reset_sample_high;
1080 show_config, 1, 1, do_show_config,
1081 "Show Marvell strapping register",
1082 "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)"