2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
34 extern void __ft_board_setup(void *blob, bd_t *bd);
38 /* fpga configuration data - generated by bin2cc */
39 const unsigned char fpgadata[] =
41 #if defined(CONFIG_CPCI405_VER2)
42 # if defined(CONFIG_CPCI405AB)
43 # include "fpgadata_cpci405ab.c"
45 # include "fpgadata_cpci4052.c"
48 # include "fpgadata_cpci405.c"
53 * include common fpga code (for esd boards)
55 #include "../common/fpga.c"
56 #include "../common/auto_update.h"
58 #if defined(CONFIG_CPCI405AB)
59 au_image_t au_image[] = {
60 {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
61 {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
62 {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
63 {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
64 {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
67 #if defined(CONFIG_CPCI405_VER2)
68 au_image_t au_image[] = {
69 {"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
70 {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
71 {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
72 {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
73 {"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
76 au_image_t au_image[] = {
77 {"cpci405/preinst.img", 0, -1, AU_SCRIPT},
78 {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
79 {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
80 {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
81 {"cpci405/postinst.img", 0, 0, AU_SCRIPT},
86 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
89 int cpci405_version(void);
90 int gunzip(void *, int, unsigned char *, unsigned long *);
91 void lxt971_no_sleep(void);
93 int board_early_init_f(void)
95 #ifndef CONFIG_CPCI405_VER2
101 /* set up serial port with default baudrate */
103 gd->baudrate = CONFIG_BAUDRATE;
109 * First pull fpga-prg pin low,
110 * to disable fpga logic (on version 2 board)
112 out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
113 out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
114 out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
115 out32(GPIO0_OR, 0); /* pull prg low */
120 #ifndef CONFIG_CPCI405_VER2
121 if (cpci405_version() == 1) {
122 status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
124 /* booting FPGA failed */
126 /* set up serial port with default baudrate */
128 gd->baudrate = CONFIG_BAUDRATE;
132 printf("\nFPGA: Booting failed ");
134 case ERROR_FPGA_PRG_INIT_LOW:
135 printf("(Timeout: INIT not low after "
136 "asserting PROGRAM*)\n ");
138 case ERROR_FPGA_PRG_INIT_HIGH:
139 printf("(Timeout: INIT not high after "
140 "deasserting PROGRAM*)\n ");
142 case ERROR_FPGA_PRG_DONE:
143 printf("(Timeout: DONE not high after "
144 "programming FPGA)\n ");
148 /* display infos on fpgaimage */
150 for (i = 0; i < 4; i++) {
151 len = fpgadata[index];
152 printf("FPGA: %s\n", &(fpgadata[index + 1]));
157 for (i = 20; i > 0; i--) {
158 printf("Rebooting in %2d seconds \r",i);
159 for (index = 0; index < 1000; index++)
163 do_reset(NULL, 0, 0, NULL);
166 #endif /* !CONFIG_CPCI405_VER2 */
169 * IRQ 0-15 405GP internally generated; active high; level sensitive
170 * IRQ 16 405GP internally generated; active low; level sensitive
172 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
173 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
174 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
175 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
176 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
177 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
178 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
180 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
181 mtdcr(uicer, 0x00000000); /* disable all ints */
182 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
183 #if defined(CONFIG_CPCI405_6U)
184 if (cpci405_version() == 3) {
185 mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
187 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
190 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
192 mtdcr(uictr, 0x10000000); /* set int trigger levels */
193 mtdcr(uicvcr, 0x00000001); /* set vect base=0,
194 * INT0 highest priority */
195 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
202 #if defined(CONFIG_CPCI405_VER2)
203 return 0; /* no, board is cpci405 */
205 if ((in_8((void*)0xf0000400) == 0x00) &&
206 (in_8((void*)0xf0000401) == 0x01))
207 return 0; /* no, board is cpci405 */
209 return -1; /* yes, board is cterm-m2 */
213 int cpci405_host(void)
215 if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
216 return -1; /* yes, board is cpci405 host */
218 return 0; /* no, board is cpci405 adapter */
221 int cpci405_version(void)
223 unsigned long cntrl0Reg;
227 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
229 cntrl0Reg = mfdcr(cntrl0);
230 mtdcr(cntrl0, cntrl0Reg | 0x03000000);
231 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
232 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
233 udelay(1000); /* wait some time before reading input */
234 value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
237 * Restore GPIO settings
239 mtdcr(cntrl0, cntrl0Reg);
243 /* CS2==1 && CS3==1 -> version 1 */
246 /* CS2==0 && CS3==1 -> version 2 */
249 /* CS2==1 && CS3==0 -> version 3 or 6U board */
252 /* CS2==0 && CS3==0 -> version 4 */
255 /* should not be reached! */
260 int misc_init_r (void)
262 unsigned long cntrl0Reg;
264 /* adjust flash start and offset */
265 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
266 gd->bd->bi_flashoffset = 0;
268 #if defined(CONFIG_CPCI405_VER2)
271 ulong len = sizeof(fpgadata);
277 * On CPCI-405 version 2 the environment is saved in eeprom!
278 * FPGA can be gzip compressed (malloc) and booted this late.
280 if (cpci405_version() >= 2) {
282 * Setup GPIO pins (CS6+CS7 as GPIO)
284 cntrl0Reg = mfdcr(cntrl0);
285 mtdcr(cntrl0, cntrl0Reg | 0x00300000);
287 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
288 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
289 (uchar *)fpgadata, &len) != 0) {
290 printf("GUNZIP ERROR - must RESET board to recover\n");
291 do_reset(NULL, 0, 0, NULL);
294 status = fpga_boot(dst, len);
296 printf("\nFPGA: Booting failed ");
298 case ERROR_FPGA_PRG_INIT_LOW:
299 printf("(Timeout: INIT not low after "
300 "asserting PROGRAM*)\n ");
302 case ERROR_FPGA_PRG_INIT_HIGH:
303 printf("(Timeout: INIT not high after "
304 "deasserting PROGRAM*)\n ");
306 case ERROR_FPGA_PRG_DONE:
307 printf("(Timeout: DONE not high after "
308 "programming FPGA)\n ");
312 /* display infos on fpgaimage */
314 for (i = 0; i < 4; i++) {
316 printf("FPGA: %s\n", &(dst[index + 1]));
321 for (i = 20; i > 0; i--) {
322 printf("Rebooting in %2d seconds \r", i);
323 for (index = 0; index < 1000; index++)
327 do_reset(NULL, 0, 0, NULL);
330 /* restore gpio/cs settings */
331 mtdcr(cntrl0, cntrl0Reg);
335 /* display infos on fpgaimage */
337 for (i = 0; i < 4; i++) {
339 printf("%s ", &(dst[index + 1]));
347 * Reset FPGA via FPGA_DATA pin
349 SET_FPGA(FPGA_PRG | FPGA_CLK);
350 udelay(1000); /* wait 1ms */
351 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
352 udelay(1000); /* wait 1ms */
354 #if defined(CONFIG_CPCI405_6U)
355 #error HIER GETH ES WEITER MIT IO ACCESSORS
356 if (cpci405_version() == 3) {
358 * Enable outputs in fpga on version 3 board
360 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
361 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
362 CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
367 out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
370 * Reset external DUART
372 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
373 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
374 CONFIG_SYS_FPGA_MODE_DUART_RESET);
376 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
377 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
378 ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
383 puts("\n*** U-Boot Version does not match Board Version!\n");
384 puts("*** CPCI-405 Version 1.x detected!\n");
385 puts("*** Please use correct U-Boot version "
386 "(CPCI405 instead of CPCI4052)!\n\n");
389 #else /* CONFIG_CPCI405_VER2 */
390 if (cpci405_version() >= 2) {
391 puts("\n*** U-Boot Version does not match Board Version!\n");
392 puts("*** CPCI-405 Board Version 2.x detected!\n");
393 puts("*** Please use correct U-Boot version "
394 "(CPCI4052 instead of CPCI405)!\n\n");
396 #endif /* CONFIG_CPCI405_VER2 */
399 * Select cts (and not dsr) on uart1
401 cntrl0Reg = mfdcr(cntrl0);
402 mtdcr(cntrl0, cntrl0Reg | 0x00001000);
408 * Check Board Identity:
413 #ifndef CONFIG_CPCI405_VER2
418 int i = getenv_r("serial#", str, sizeof(str));
424 puts("### No HW ID - assuming CPCI405");
428 ver = cpci405_version();
429 printf(" (Ver %d.x, ", ver);
435 * Read board-id and save in env-variable
437 sprintf(str, "%d", *(unsigned char *)0xf0000400);
438 setenv("boardid", str);
439 printf("CTERM-M2 - Id=%s)", str);
442 puts("PCI Host Version)");
444 puts("PCI Adapter Version)");
447 #ifndef CONFIG_CPCI405_VER2
450 /* display infos on fpgaimage */
452 for (i = 0; i < 4; i++) {
453 len = fpgadata[index];
454 printf("%s ", &(fpgadata[index + 1]));
465 #if defined(CONFIG_LXT971_NO_SLEEP)
468 * Disable sleep mode in LXT971
474 #if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
475 void ide_set_reset(int on)
478 * Assert or deassert CompactFlash Reset Pin
480 if (on) { /* assert RESET */
481 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
482 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
483 ~CONFIG_SYS_FPGA_MODE_CF_RESET);
484 } else { /* release RESET */
485 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
486 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
487 CONFIG_SYS_FPGA_MODE_CF_RESET);
491 #endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
493 #if defined(CONFIG_PCI)
494 void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
496 unsigned char int_line = 0xff;
499 * Write pci interrupt line register (cpci405 specific)
501 switch (PCI_DEV(dev) & 0x03) {
516 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
519 int pci_pre_init(struct pci_controller *hose)
521 hose->fixup_irq = cpci405_pci_fixup_irq;
524 #endif /* defined(CONFIG_PCI) */
526 #if defined(CONFIG_CPCI405AB)
527 #define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
528 CONFIG_SYS_FPGA_MODE), \
529 in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
530 CONFIG_SYS_FPGA_MODE)) | \
531 CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
533 #define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
534 CONFIG_SYS_FPGA_MODE), \
535 in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
536 CONFIG_SYS_FPGA_MODE)) & \
537 ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
539 #define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
540 CONFIG_SYS_FPGA_STATUS)) & \
541 CONFIG_SYS_FPGA_MODE_1WIRE)
544 * Generate a 1-wire reset, return 1 if no presence detect was found,
545 * return 0 otherwise.
546 * (NOTE: Does not handle alarm presence from DS2404/DS1994)
548 int OWTouchReset(void)
557 result = ONE_WIRE_GET;
564 * Send 1 a 1-wire write bit.
565 * Provide 10us recovery time.
567 void OWWriteBit(int bit)
589 * Read a bit from the 1-wire bus and return it.
590 * Provide 10us recovery time.
601 result = ONE_WIRE_GET;
607 void OWWriteByte(int data)
611 for (loop = 0; loop < 8; loop++) {
612 OWWriteBit(data & 0x01);
619 int loop, result = 0;
621 for (loop = 0; loop < 8; loop++) {
630 int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
635 unsigned char ow_id[6];
637 unsigned char ow_crc;
640 * Clear 1-wire bit (open drain with pull-up)
642 val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
643 CONFIG_SYS_FPGA_MODE));
644 val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
645 out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
646 CONFIG_SYS_FPGA_MODE), val);
648 result = OWTouchReset();
650 puts("No 1-wire device detected!\n");
652 OWWriteByte(0x33); /* send read rom command */
653 OWReadByte(); /* skip family code ( == 0x01) */
654 for (i = 0; i < 6; i++)
655 ow_id[i] = OWReadByte();
656 ow_crc = OWReadByte(); /* read crc */
658 sprintf(str, "%08X%04X",
659 *(unsigned int *)&ow_id[0],
660 *(unsigned short *)&ow_id[4]);
661 printf("Setting environment variable 'ow_id' to %s\n", str);
662 setenv("ow_id", str);
667 onewire, 1, 1, do_onewire,
668 "onewire - Read 1-write ID\n",
672 #define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
673 #define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
676 * Write backplane ip-address...
678 int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
687 buf = malloc(CONFIG_ENV_SIZE_2);
688 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
689 (uchar *)buf, CONFIG_ENV_SIZE_2))
690 puts("\nError reading backplane EEPROM!\n");
692 crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
693 if (crc != *(ulong *)buf) {
694 printf("ERROR: crc mismatch %08lx %08lx\n",
702 ptr = strstr(buf+4, "bp_ip=");
704 printf("ERROR: bp_ip not found!\n");
708 ipaddr = string_to_ip(ptr);
711 * Update whole ip-addr
713 bd->bi_ip_addr = ipaddr;
714 sprintf(str, "%ld.%ld.%ld.%ld",
715 (bd->bi_ip_addr & 0xff000000) >> 24,
716 (bd->bi_ip_addr & 0x00ff0000) >> 16,
717 (bd->bi_ip_addr & 0x0000ff00) >> 8,
718 (bd->bi_ip_addr & 0x000000ff));
719 setenv("ipaddr", str);
720 printf("Updated ip_addr from bp_eeprom to %s!\n", str);
728 getbpip, 1, 1, do_get_bpip,
729 "getbpip - Update IP-Address with Backplane IP-Address\n",
734 * Set and print backplane ip...
736 int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
747 printf("Setting bp_ip to %s\n", argv[1]);
748 buf = malloc(CONFIG_ENV_SIZE_2);
749 memset(buf, 0, CONFIG_ENV_SIZE_2);
750 sprintf(str, "bp_ip=%s", argv[1]);
752 crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
755 if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
756 0, (uchar *)buf, CONFIG_ENV_SIZE_2))
757 puts("\nError writing backplane EEPROM!\n");
764 setbpip, 2, 1, do_set_bpip,
765 "setbpip - Write Backplane IP-Address\n",
769 #endif /* CONFIG_CPCI405AB */