2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
30 /* ------------------------------------------------------------------------- */
36 /* fpga configuration data - generated by bin2cc */
37 const unsigned char fpgadata[] =
39 #ifdef CONFIG_CPCI405_VER2
40 # include "fpgadata_cpci4052.c"
42 # include "fpgadata_cpci405.c"
47 * include common fpga code (for esd boards)
49 #include "../common/fpga.c"
53 int cpci405_version(void);
54 int gunzip(void *, int, unsigned char *, int *);
57 int board_pre_init (void)
59 #ifndef CONFIG_CPCI405_VER2
65 DECLARE_GLOBAL_DATA_PTR;
67 /* set up serial port with default baudrate */
69 gd->baudrate = CONFIG_BAUDRATE;
75 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
77 out32(IBM405GP_GPIO0_ODR, 0x00000000); /* no open drain pins */
78 out32(IBM405GP_GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
79 out32(IBM405GP_GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
80 out32(IBM405GP_GPIO0_OR, 0); /* pull prg low */
85 #ifndef CONFIG_CPCI405_VER2
86 if (cpci405_version() == 1) {
87 status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
89 /* booting FPGA failed */
91 DECLARE_GLOBAL_DATA_PTR;
93 /* set up serial port with default baudrate */
95 gd->baudrate = CONFIG_BAUDRATE;
99 printf("\nFPGA: Booting failed ");
101 case ERROR_FPGA_PRG_INIT_LOW:
102 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
104 case ERROR_FPGA_PRG_INIT_HIGH:
105 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
107 case ERROR_FPGA_PRG_DONE:
108 printf("(Timeout: DONE not high after programming FPGA)\n ");
112 /* display infos on fpgaimage */
114 for (i=0; i<4; i++) {
115 len = fpgadata[index];
116 printf("FPGA: %s\n", &(fpgadata[index+1]));
121 for (i=20; i>0; i--) {
122 printf("Rebooting in %2d seconds \r",i);
123 for (index=0;index<1000;index++)
127 do_reset(NULL, 0, 0, NULL);
130 #endif /* !CONFIG_CPCI405_VER2 */
133 * IRQ 0-15 405GP internally generated; active high; level sensitive
134 * IRQ 16 405GP internally generated; active low; level sensitive
136 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
137 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
138 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
139 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
140 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
141 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
142 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
144 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
145 mtdcr(uicer, 0x00000000); /* disable all ints */
146 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
147 if (cpci405_version() == 3) {
148 mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
150 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
152 mtdcr(uictr, 0x10000000); /* set int trigger levels */
153 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
154 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
160 /* ------------------------------------------------------------------------- */
164 #ifdef CONFIG_CPCI405_VER2
165 return 0; /* no, board is cpci405 */
167 if ((*(unsigned char *)0xf0000400 == 0x00) &&
168 (*(unsigned char *)0xf0000401 == 0x01))
169 return 0; /* no, board is cpci405 */
171 return -1; /* yes, board is cterm-m2 */
176 int cpci405_host(void)
178 if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
179 return -1; /* yes, board is cpci405 host */
181 return 0; /* no, board is cpci405 adapter */
185 int cpci405_version(void)
187 unsigned long cntrl0Reg;
191 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
193 cntrl0Reg = mfdcr(cntrl0);
194 mtdcr(cntrl0, cntrl0Reg | 0x03000000);
195 out32(IBM405GP_GPIO0_ODR, in32(IBM405GP_GPIO0_ODR) & ~0x00180000);
196 out32(IBM405GP_GPIO0_TCR, in32(IBM405GP_GPIO0_TCR) & ~0x00180000);
197 udelay(1000); /* wait some time before reading input */
198 value = in32(IBM405GP_GPIO0_IR) & 0x00180000; /* get config bits */
201 * Restore GPIO settings
203 mtdcr(cntrl0, cntrl0Reg);
207 /* CS2==1 && CS3==1 -> version 1 */
210 /* CS2==0 && CS3==1 -> version 2 */
213 /* CS2==1 && CS3==0 -> version 3 */
216 /* CS2==0 && CS3==0 -> version 4 */
219 /* should not be reached! */
225 int misc_init_f (void)
227 return 0; /* dummy implementation */
231 int misc_init_r (void)
233 DECLARE_GLOBAL_DATA_PTR;
236 char * tmp; /* Temporary char pointer */
238 #ifdef CONFIG_CPCI405_VER2
240 ulong len = sizeof(fpgadata);
244 unsigned long cntrl0Reg;
247 * On CPCI-405 version 2 the environment is saved in eeprom!
248 * FPGA can be gzip compressed (malloc) and booted this late.
251 if (cpci405_version() >= 2) {
253 * Setup GPIO pins (CS6+CS7 as GPIO)
255 cntrl0Reg = mfdcr(cntrl0);
256 mtdcr(cntrl0, cntrl0Reg | 0x00300000);
258 dst = malloc(CFG_FPGA_MAX_SIZE);
259 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
260 printf ("GUNZIP ERROR - must RESET board to recover\n");
261 do_reset (NULL, 0, 0, NULL);
264 status = fpga_boot(dst, len);
266 printf("\nFPGA: Booting failed ");
268 case ERROR_FPGA_PRG_INIT_LOW:
269 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
271 case ERROR_FPGA_PRG_INIT_HIGH:
272 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
274 case ERROR_FPGA_PRG_DONE:
275 printf("(Timeout: DONE not high after programming FPGA)\n ");
279 /* display infos on fpgaimage */
281 for (i=0; i<4; i++) {
283 printf("FPGA: %s\n", &(dst[index+1]));
288 for (i=20; i>0; i--) {
289 printf("Rebooting in %2d seconds \r",i);
290 for (index=0;index<1000;index++)
294 do_reset(NULL, 0, 0, NULL);
297 /* restore gpio/cs settings */
298 mtdcr(cntrl0, cntrl0Reg);
302 /* display infos on fpgaimage */
304 for (i=0; i<4; i++) {
306 printf("%s ", &(dst[index+1]));
314 * Reset FPGA via FPGA_DATA pin
316 SET_FPGA(FPGA_PRG | FPGA_CLK);
317 udelay(1000); /* wait 1ms */
318 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
319 udelay(1000); /* wait 1ms */
321 if (cpci405_version() == 3) {
322 volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
323 volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
326 * Enable outputs in fpga on version 3 board
328 *fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT;
336 * Reset external DUART
338 *fpga_mode |= CFG_FPGA_MODE_DUART_RESET;
340 *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
344 puts("\n*** U-Boot Version does not match Board Version!\n");
345 puts("*** CPCI-405 Version 1.x detected!\n");
346 puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
349 #else /* CONFIG_CPCI405_VER2 */
352 * Generate last byte of ip-addr from code-plug @ 0xf0000400
356 unsigned char ipbyte = *(unsigned char *)0xf0000400;
359 * Only overwrite ip-addr with allowed values
361 if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
362 bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
363 sprintf(str, "%ld.%ld.%ld.%ld",
364 (bd->bi_ip_addr & 0xff000000) >> 24,
365 (bd->bi_ip_addr & 0x00ff0000) >> 16,
366 (bd->bi_ip_addr & 0x0000ff00) >> 8,
367 (bd->bi_ip_addr & 0x000000ff));
368 setenv("ipaddr", str);
372 if (cpci405_version() >= 2) {
373 puts("\n*** U-Boot Version does not match Board Version!\n");
374 puts("*** CPCI-405 Board Version 2.x detected!\n");
375 puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
378 #endif /* CONFIG_CPCI405_VER2 */
381 * Write ethernet addr in NVRAM for VxWorks
383 tmp = (char *)CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS;
384 memcpy( (char *)tmp, (char *)&bd->bi_enetaddr[0], 6 );
390 * Check Board Identity:
393 int checkboard (void)
395 #ifndef CONFIG_CPCI405_VER2
399 unsigned char str[64];
400 int i = getenv_r ("serial#", str, sizeof(str));
406 puts ("### No HW ID - assuming CPCI405");
411 ver = cpci405_version();
412 printf(" (Ver %d.x, ", ver);
414 #if 0 /* test-only */
416 volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1;
418 if (*fpga_status & CFG_FPGA_STATUS_FLASH) {
419 puts ("FLASH Bank B, ");
421 puts ("FLASH Bank A, ");
427 printf("CTERM-M2 - Id=0x%02x)", *(unsigned char *)0xf0000400);
429 if (cpci405_host()) {
430 puts ("PCI Host Version)");
432 puts ("PCI Adapter Version)");
436 #ifndef CONFIG_CPCI405_VER2
439 /* display infos on fpgaimage */
441 for (i=0; i<4; i++) {
442 len = fpgadata[index];
443 printf("%s ", &(fpgadata[index+1]));
453 /* ------------------------------------------------------------------------- */
455 long int initdram (int board_type)
459 mtdcr(memcfga, mem_mb0cf);
460 val = mfdcr(memcfgd);
463 printf("\nmb0cf=%x\n", val); /* test-only */
464 printf("strap=%x\n", mfdcr(strap)); /* test-only */
467 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
470 /* ------------------------------------------------------------------------- */
474 /* TODO: XXX XXX XXX */
475 printf ("test: 16 MB - ok\n");
480 /* ------------------------------------------------------------------------- */
482 #ifdef CONFIG_CPCI405_VER2
483 #ifdef CONFIG_IDE_RESET
485 void ide_set_reset(int on)
487 volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
490 * Assert or deassert CompactFlash Reset Pin
492 if (on) { /* assert RESET */
493 *fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET);
494 } else { /* release RESET */
495 *fpga_mode |= CFG_FPGA_MODE_CF_RESET;
499 #endif /* CONFIG_IDE_RESET */
500 #endif /* CONFIG_CPCI405_VER2 */
502 /* ------------------------------------------------------------------------- */