2 * (C) Copyright 2001-2003
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
29 /* ------------------------------------------------------------------------- */
32 #define DBG(x...) printf(x)
40 # define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output)*/
41 # define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */
42 # define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */
43 # define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */
44 # define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */
46 # define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
47 # define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
48 # define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
49 # define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
50 # define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
53 #define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
54 #define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
55 #define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
57 #define SET_FPGA(data) out32(GPIO0_OR, data)
59 #define FPGA_WRITE_1 { \
60 SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
61 SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
62 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
63 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
65 #define FPGA_WRITE_0 { \
66 SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
67 SET_FPGA(FPGA_PRG); /* set data to 0 */ \
68 SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
69 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
72 static int fpga_boot(unsigned char *fpgadata, int size)
76 #ifdef CFG_FPGA_SPARTAN2
83 /* display infos on fpgaimage */
87 len = fpgadata[index];
88 DBG("FPGA: %s\n", &(fpgadata[index+1]));
92 #ifdef CFG_FPGA_SPARTAN2
93 /* search for preamble 0xFFFFFFFF */
96 if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) &&
97 (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff))
98 break; /* preamble found */
103 /* search for preamble 0xFF2X */
104 for (index = 0; index < size-1 ; index++)
106 if ((fpgadata[index] == 0xff) && ((fpgadata[index+1] & 0xf0) == 0x30))
112 DBG("FPGA: configdata starts at position 0x%x\n",index);
113 DBG("FPGA: length of fpga-data %d\n", size-index);
116 * Setup port pins for fpga programming
118 out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
119 out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
120 out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */
122 DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
123 DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
126 * Init fpga by asserting and deasserting PROGRAM*
128 SET_FPGA(FPGA_CLK | FPGA_DATA);
130 /* Wait for FPGA init line low */
132 while (in32(GPIO0_IR) & FPGA_INIT)
134 udelay(1000); /* wait 1ms */
135 /* Check for timeout - 100us max, so use 3ms */
138 DBG("FPGA: Booting failed!\n");
139 return ERROR_FPGA_PRG_INIT_LOW;
143 DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
144 DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
146 /* deassert PROGRAM* */
147 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
149 /* Wait for FPGA end of init period . */
151 while (!(in32(GPIO0_IR) & FPGA_INIT))
153 udelay(1000); /* wait 1ms */
154 /* Check for timeout */
157 DBG("FPGA: Booting failed!\n");
158 return ERROR_FPGA_PRG_INIT_HIGH;
162 DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
163 DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
165 DBG("write configuration data into fpga\n");
166 /* write configuration-data into fpga... */
168 #ifdef CFG_FPGA_SPARTAN2
170 * Load uncompressed image into fpga
172 for (i=index; i<size; i++)
176 if ((fpgadata[i] & 0x80) == 0x80)
189 FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
190 FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
191 FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_1; FPGA_WRITE_0;
192 FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0;
196 ** Code 1 .. maxOnes : n '1's followed by '0'
197 ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
198 ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
202 for (i=index; i<size; i++)
205 if ((b >= 1) && (b <= MAX_ONES))
207 for(bit=0; bit<b; bit++)
213 else if (b == (MAX_ONES+1))
215 for(bit=1; bit<b; bit++)
220 else if ((b >= (MAX_ONES+2)) && (b <= 254))
222 for(bit=0; bit<(b-(MAX_ONES+2)); bit++)
235 DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
236 DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
239 * Check if fpga's DONE signal - correctly booted ?
242 /* Wait for FPGA end of programming period . */
244 while (!(in32(GPIO0_IR) & FPGA_DONE))
246 udelay(1000); /* wait 1ms */
247 /* Check for timeout */
250 DBG("FPGA: Booting failed!\n");
251 return ERROR_FPGA_PRG_DONE;
255 DBG("FPGA: Booting successful!\n");