1 // SPDX-License-Identifier: GPL-2.0+
5 * Generated code from MX8M_DDR_tool
6 * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
10 #include <asm/arch/ddr.h>
11 #include <asm/arch/lpddr4_define.h>
13 struct dram_cfg_param ddr_ddrc_cfg[] = {
14 /* Initialize DDRC registers */
17 {0x3d400000, 0xa1080020},
19 {0x3d400024, 0x3a980},
20 {0x3d400064, 0x5b0087},
21 {0x3d4000d0, 0xc00305ba},
22 {0x3d4000d4, 0x940000},
23 {0x3d4000dc, 0xd4002d},
24 {0x3d4000e0, 0x210000},
25 {0x3d4000e8, 0x44004d},
26 {0x3d4000ec, 0x14004d},
27 {0x3d400100, 0x191f1920},
28 {0x3d400104, 0x60630},
29 {0x3d40010c, 0xb0b000},
30 {0x3d400110, 0xe04080e},
31 {0x3d400114, 0x2040c0c},
32 {0x3d400118, 0x1010007},
34 {0x3d400130, 0x20600},
35 {0x3d400134, 0xc100002},
37 {0x3d400144, 0x96004b},
38 {0x3d400180, 0x2ee0017},
39 {0x3d400184, 0x2605b8e},
41 {0x3d400190, 0x497820a},
42 {0x3d400194, 0x80303},
44 {0x3d4001a0, 0xe0400018},
45 {0x3d4001a4, 0xdf00e4},
46 {0x3d4001a8, 0x80000000},
51 {0x3d400108, 0x70e1617},
55 {0x3d400204, 0x80808},
56 {0x3d400214, 0x7070707},
57 {0x3d400218, 0xf070707},
58 {0x3d400250, 0x29001701},
60 {0x3d40025c, 0x4000030},
61 {0x3d400264, 0x900093e7},
62 {0x3d40026c, 0x2005574},
65 {0x3d400494, 0x2100e07},
66 {0x3d400498, 0x620096},
67 {0x3d40049c, 0x1100e07},
68 {0x3d4004a0, 0xc8012c},
71 {0x3d402050, 0x20d040},
72 {0x3d402064, 0xc0012},
73 {0x3d4020dc, 0x840000},
74 {0x3d4020e0, 0x310000},
75 {0x3d4020e8, 0x66004d},
76 {0x3d4020ec, 0x16004d},
77 {0x3d402100, 0xa050305},
78 {0x3d402104, 0x30407},
79 {0x3d402108, 0x203060b},
80 {0x3d40210c, 0x505000},
81 {0x3d402110, 0x2040202},
82 {0x3d402114, 0x2030202},
83 {0x3d402118, 0x1010004},
85 {0x3d402130, 0x20300},
86 {0x3d402134, 0xa100002},
88 {0x3d402144, 0x14000a},
89 {0x3d402180, 0x640004},
90 {0x3d402190, 0x3818200},
91 {0x3d402194, 0x80303},
95 {0x3d403050, 0x20d040},
96 {0x3d403064, 0x30005},
97 {0x3d4030dc, 0x840000},
98 {0x3d4030e0, 0x310000},
99 {0x3d4030e8, 0x66004d},
100 {0x3d4030ec, 0x16004d},
101 {0x3d403100, 0xa020102},
102 {0x3d403104, 0x30404},
103 {0x3d403108, 0x203060b},
104 {0x3d40310c, 0x505000},
105 {0x3d403110, 0x2040202},
106 {0x3d403114, 0x2030202},
107 {0x3d403118, 0x1010004},
109 {0x3d403130, 0x20300},
110 {0x3d403134, 0xa100002},
112 {0x3d403144, 0x50003},
113 {0x3d403180, 0x190004},
114 {0x3d403190, 0x3818200},
115 {0x3d403194, 0x80303},
120 /* PHY Initialize Configuration */
121 struct dram_cfg_param ddr_ddrphy_cfg[] = {
324 /* ddr phy trained csr */
325 struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
1047 /* P0 message block paremeter for training firmware */
1048 struct dram_cfg_param ddr_fsp0_cfg[] = {
1086 /* P1 message block paremeter for training firmware */
1087 struct dram_cfg_param ddr_fsp1_cfg[] = {
1126 /* P2 message block paremeter for training firmware */
1127 struct dram_cfg_param ddr_fsp2_cfg[] = {
1166 /* P0 2D message block paremeter for training firmware */
1167 struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1206 /* DRAM PHY init engine image */
1207 struct dram_cfg_param ddr_phy_pie[] = {
1802 struct dram_fsp_msg ddr_dram_fsp_msg[] = {
1806 .fw_type = FW_1D_IMAGE,
1807 .fsp_cfg = ddr_fsp0_cfg,
1808 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
1813 .fw_type = FW_1D_IMAGE,
1814 .fsp_cfg = ddr_fsp1_cfg,
1815 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
1820 .fw_type = FW_1D_IMAGE,
1821 .fsp_cfg = ddr_fsp2_cfg,
1822 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
1827 .fw_type = FW_2D_IMAGE,
1828 .fsp_cfg = ddr_fsp0_2d_cfg,
1829 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
1833 /* ddr timing config params */
1834 struct dram_timing_info dram_timing = {
1835 .ddrc_cfg = ddr_ddrc_cfg,
1836 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
1837 .ddrphy_cfg = ddr_ddrphy_cfg,
1838 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
1839 .fsp_msg = ddr_dram_fsp_msg,
1840 .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
1841 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1842 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
1843 .ddrphy_pie = ddr_phy_pie,
1844 .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
1845 .fsp_table = { 3000, 400, 100, },