board/engicam/icorem6_rqs/icorem6_rqs.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <mmc.h>
  11
  12 #include <asm/io.h>
  13 #include <asm/gpio.h>
  14 #include <linux/sizes.h>
  15
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/iomux.h>
  19 #include <asm/arch/mx6-pins.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/imx-common/iomux-v3.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  26         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  27         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  28
  29 static iomux_v3_cfg_t const uart4_pads[] = {
  30         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  31         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  32 };
  33
  34 int board_early_init_f(void)
  35 {
  36         SETUP_IOMUX_PADS(uart4_pads);
  37
  38         return 0;
  39 }
  40
  41 int board_init(void)
  42 {
  43         /* Address of boot parameters */
  44         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  45
  46         return 0;
  47 }
  48
  49 #ifdef CONFIG_ENV_IS_IN_MMC
  50 static void mmc_late_init(void)
  51 {
  52         char cmd[32];
  53         char mmcblk[32];
  54         u32 dev_no = mmc_get_env_dev();
  55
  56         setenv_ulong("mmcdev", dev_no);
  57
  58         /* Set mmcblk env */
  59         sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
  60         setenv("mmcroot", mmcblk);
  61
  62         sprintf(cmd, "mmc dev %d", dev_no);
  63         run_command(cmd, 0);
  64 }
  65 #endif
  66
  67 int board_late_init(void)
  68 {
  69         switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
  70                         IMX6_BMODE_SHIFT) {
  71         case IMX6_BMODE_SD:
  72         case IMX6_BMODE_ESD:
  73         case IMX6_BMODE_MMC:
  74         case IMX6_BMODE_EMMC:
  75 #ifdef CONFIG_ENV_IS_IN_MMC
  76                 mmc_late_init();
  77 #endif
  78                 setenv("modeboot", "mmcboot");
  79                 break;
  80         default:
  81                 setenv("modeboot", "");
  82                 break;
  83         }
  84
  85         return 0;
  86 }
  87
  88 int dram_init(void)
  89 {
  90         gd->ram_size = imx_ddr_size();
  91
  92         return 0;
  93 }
  94
  95 #ifdef CONFIG_SPL_BUILD
  96 #include <libfdt.h>
  97 #include <spl.h>
  98
  99 #include <asm/arch/crm_regs.h>
 100 #include <asm/arch/mx6-ddr.h>
 101
 102 /* MMC board initialization is needed till adding DM support in SPL */
 103 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
 104 #include <mmc.h>
 105 #include <fsl_esdhc.h>
 106
 107 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 108         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_HIGH |               \
 109         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 110
 111 static iomux_v3_cfg_t const usdhc3_pads[] = {
 112         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 113         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 114         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 115         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 116         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 117         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 118 };
 119
 120 static iomux_v3_cfg_t const usdhc4_pads[] = {
 121         IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 122         IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 123         IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 124         IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 125         IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 126         IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 127         IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 128         IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 129         IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 130         IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 131 };
 132
 133 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 134         {USDHC3_BASE_ADDR, 1, 4},
 135         {USDHC4_BASE_ADDR, 1, 8},
 136 };
 137
 138 int board_mmc_getcd(struct mmc *mmc)
 139 {
 140         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 141         int ret = 0;
 142
 143         switch (cfg->esdhc_base) {
 144         case USDHC3_BASE_ADDR:
 145         case USDHC4_BASE_ADDR:
 146                 ret = 1;
 147                 break;
 148         }
 149
 150         return ret;
 151 }
 152
 153 int board_mmc_init(bd_t *bis)
 154 {
 155         int i, ret;
 156
 157         /*
 158         * According to the board_mmc_init() the following map is done:
 159         * (U-boot device node)    (Physical Port)
 160         * mmc0                  USDHC3
 161         * mmc1                  USDHC4
 162         */
 163         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 164                 switch (i) {
 165                 case 0:
 166                         SETUP_IOMUX_PADS(usdhc3_pads);
 167                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 168                         break;
 169                 case 1:
 170                         SETUP_IOMUX_PADS(usdhc4_pads);
 171                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 172                         break;
 173                 default:
 174                         printf("Warning - USDHC%d controller not supporting\n",
 175                                i + 1);
 176                         return 0;
 177                 }
 178
 179                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 180                 if (ret) {
 181                         printf("Warning: failed to initialize mmc dev %d\n", i);
 182                         return ret;
 183                 }
 184         }
 185
 186         return 0;
 187 }
 188
 189 #ifdef CONFIG_ENV_IS_IN_MMC
 190 void board_boot_order(u32 *spl_boot_list)
 191 {
 192         u32 bmode = imx6_src_get_boot_mode();
 193         u8 boot_dev = BOOT_DEVICE_MMC1;
 194
 195         switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
 196         case IMX6_BMODE_SD:
 197         case IMX6_BMODE_ESD:
 198                 /* SD/eSD - BOOT_DEVICE_MMC1 */
 199                 break;
 200         case IMX6_BMODE_MMC:
 201         case IMX6_BMODE_EMMC:
 202                 /* MMC/eMMC */
 203                 boot_dev = BOOT_DEVICE_MMC2;
 204                 break;
 205         default:
 206                 /* Default - BOOT_DEVICE_MMC1 */
 207                 printf("Wrong board boot order\n");
 208                 break;
 209         }
 210
 211         spl_boot_list[0] = boot_dev;
 212 }
 213 #endif
 214 #endif
 215
 216 /*
 217  * Driving strength:
 218  *   0x30 == 40 Ohm
 219  *   0x28 == 48 Ohm
 220  */
 221
 222 #define IMX6DQ_DRIVE_STRENGTH           0x30
 223 #define IMX6SDL_DRIVE_STRENGTH          0x28
 224
 225 /* configure MX6Q/DUAL mmdc DDR io registers */
 226 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 227         .dram_sdqs0 = 0x28,
 228         .dram_sdqs1 = 0x28,
 229         .dram_sdqs2 = 0x28,
 230         .dram_sdqs3 = 0x28,
 231         .dram_sdqs4 = 0x28,
 232         .dram_sdqs5 = 0x28,
 233         .dram_sdqs6 = 0x28,
 234         .dram_sdqs7 = 0x28,
 235         .dram_dqm0 = 0x28,
 236         .dram_dqm1 = 0x28,
 237         .dram_dqm2 = 0x28,
 238         .dram_dqm3 = 0x28,
 239         .dram_dqm4 = 0x28,
 240         .dram_dqm5 = 0x28,
 241         .dram_dqm6 = 0x28,
 242         .dram_dqm7 = 0x28,
 243         .dram_cas = 0x30,
 244         .dram_ras = 0x30,
 245         .dram_sdclk_0 = 0x30,
 246         .dram_sdclk_1 = 0x30,
 247         .dram_reset = 0x30,
 248         .dram_sdcke0 = 0x3000,
 249         .dram_sdcke1 = 0x3000,
 250         .dram_sdba2 = 0x00000000,
 251         .dram_sdodt0 = 0x30,
 252         .dram_sdodt1 = 0x30,
 253 };
 254
 255 /* configure MX6Q/DUAL mmdc GRP io registers */
 256 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 257         .grp_b0ds = 0x30,
 258         .grp_b1ds = 0x30,
 259         .grp_b2ds = 0x30,
 260         .grp_b3ds = 0x30,
 261         .grp_b4ds = 0x30,
 262         .grp_b5ds = 0x30,
 263         .grp_b6ds = 0x30,
 264         .grp_b7ds = 0x30,
 265         .grp_addds = 0x30,
 266         .grp_ddrmode_ctl = 0x00020000,
 267         .grp_ddrpke = 0x00000000,
 268         .grp_ddrmode = 0x00020000,
 269         .grp_ctlds = 0x30,
 270         .grp_ddr_type = 0x000c0000,
 271 };
 272
 273 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 274 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 275         .dram_sdclk_0 = 0x30,
 276         .dram_sdclk_1 = 0x30,
 277         .dram_cas = 0x30,
 278         .dram_ras = 0x30,
 279         .dram_reset = 0x30,
 280         .dram_sdcke0 = 0x30,
 281         .dram_sdcke1 = 0x30,
 282         .dram_sdba2 = 0x00000000,
 283         .dram_sdodt0 = 0x30,
 284         .dram_sdodt1 = 0x30,
 285         .dram_sdqs0 = 0x28,
 286         .dram_sdqs1 = 0x28,
 287         .dram_sdqs2 = 0x28,
 288         .dram_sdqs3 = 0x28,
 289         .dram_sdqs4 = 0x28,
 290         .dram_sdqs5 = 0x28,
 291         .dram_sdqs6 = 0x28,
 292         .dram_sdqs7 = 0x28,
 293         .dram_dqm0 = 0x28,
 294         .dram_dqm1 = 0x28,
 295         .dram_dqm2 = 0x28,
 296         .dram_dqm3 = 0x28,
 297         .dram_dqm4 = 0x28,
 298         .dram_dqm5 = 0x28,
 299         .dram_dqm6 = 0x28,
 300         .dram_dqm7 = 0x28,
 301 };
 302
 303 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 304 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 305         .grp_ddr_type = 0x000c0000,
 306         .grp_ddrmode_ctl = 0x00020000,
 307         .grp_ddrpke = 0x00000000,
 308         .grp_addds = 0x30,
 309         .grp_ctlds = 0x30,
 310         .grp_ddrmode = 0x00020000,
 311         .grp_b0ds = 0x28,
 312         .grp_b1ds = 0x28,
 313         .grp_b2ds = 0x28,
 314         .grp_b3ds = 0x28,
 315         .grp_b4ds = 0x28,
 316         .grp_b5ds = 0x28,
 317         .grp_b6ds = 0x28,
 318         .grp_b7ds = 0x28,
 319 };
 320
 321 /* mt41j256 */
 322 static struct mx6_ddr3_cfg mt41j256 = {
 323         .mem_speed = 1066,
 324         .density = 2,
 325         .width = 16,
 326         .banks = 8,
 327         .rowaddr = 13,
 328         .coladdr = 10,
 329         .pagesz = 2,
 330         .trcd = 1375,
 331         .trcmin = 4875,
 332         .trasmin = 3500,
 333         .SRT = 0,
 334 };
 335
 336 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
 337         .p0_mpwldectrl0 = 0x000E0009,
 338         .p0_mpwldectrl1 = 0x0018000E,
 339         .p1_mpwldectrl0 = 0x00000007,
 340         .p1_mpwldectrl1 = 0x00000000,
 341         .p0_mpdgctrl0 = 0x43280334,
 342         .p0_mpdgctrl1 = 0x031C0314,
 343         .p1_mpdgctrl0 = 0x4318031C,
 344         .p1_mpdgctrl1 = 0x030C0258,
 345         .p0_mprddlctl = 0x3E343A40,
 346         .p1_mprddlctl = 0x383C3844,
 347         .p0_mpwrdlctl = 0x40404440,
 348         .p1_mpwrdlctl = 0x4C3E4446,
 349 };
 350
 351 /* DDR 64bit */
 352 static struct mx6_ddr_sysinfo mem_q = {
 353         .ddr_type       = DDR_TYPE_DDR3,
 354         .dsize          = 2,
 355         .cs1_mirror     = 0,
 356         /* config for full 4GB range so that get_mem_size() works */
 357         .cs_density     = 32,
 358         .ncs            = 1,
 359         .bi_on          = 1,
 360         .rtt_nom        = 2,
 361         .rtt_wr         = 2,
 362         .ralat          = 5,
 363         .walat          = 0,
 364         .mif3_mode      = 3,
 365         .rst_to_cke     = 0x23,
 366         .sde_to_rst     = 0x10,
 367 };
 368
 369 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
 370         .p0_mpwldectrl0 = 0x001F0024,
 371         .p0_mpwldectrl1 = 0x00110018,
 372         .p1_mpwldectrl0 = 0x001F0024,
 373         .p1_mpwldectrl1 = 0x00110018,
 374         .p0_mpdgctrl0 = 0x4230022C,
 375         .p0_mpdgctrl1 = 0x02180220,
 376         .p1_mpdgctrl0 = 0x42440248,
 377         .p1_mpdgctrl1 = 0x02300238,
 378         .p0_mprddlctl = 0x44444A48,
 379         .p1_mprddlctl = 0x46484A42,
 380         .p0_mpwrdlctl = 0x38383234,
 381         .p1_mpwrdlctl = 0x3C34362E,
 382 };
 383
 384 /* DDR 64bit 1GB */
 385 static struct mx6_ddr_sysinfo mem_dl = {
 386         .dsize          = 2,
 387         .cs1_mirror     = 0,
 388         /* config for full 4GB range so that get_mem_size() works */
 389         .cs_density     = 32,
 390         .ncs            = 1,
 391         .bi_on          = 1,
 392         .rtt_nom        = 1,
 393         .rtt_wr         = 1,
 394         .ralat          = 5,
 395         .walat          = 0,
 396         .mif3_mode      = 3,
 397         .rst_to_cke     = 0x23,
 398         .sde_to_rst     = 0x10,
 399 };
 400
 401 /* DDR 32bit 512MB */
 402 static struct mx6_ddr_sysinfo mem_s = {
 403         .dsize          = 1,
 404         .cs1_mirror     = 0,
 405         /* config for full 4GB range so that get_mem_size() works */
 406         .cs_density     = 32,
 407         .ncs            = 1,
 408         .bi_on          = 1,
 409         .rtt_nom        = 1,
 410         .rtt_wr         = 1,
 411         .ralat          = 5,
 412         .walat          = 0,
 413         .mif3_mode      = 3,
 414         .rst_to_cke     = 0x23,
 415         .sde_to_rst     = 0x10,
 416 };
 417
 418 static void ccgr_init(void)
 419 {
 420         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 421
 422         writel(0x00003F3F, &ccm->CCGR0);
 423         writel(0x0030FC00, &ccm->CCGR1);
 424         writel(0x000FC000, &ccm->CCGR2);
 425         writel(0x3F300000, &ccm->CCGR3);
 426         writel(0xFF00F300, &ccm->CCGR4);
 427         writel(0x0F0000C3, &ccm->CCGR5);
 428         writel(0x000003CC, &ccm->CCGR6);
 429 }
 430
 431 static void gpr_init(void)
 432 {
 433         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 434
 435         /* enable AXI cache for VDOA/VPU/IPU */
 436         writel(0xF00000CF, &iomux->gpr[4]);
 437         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 438         writel(0x007F007F, &iomux->gpr[6]);
 439         writel(0x007F007F, &iomux->gpr[7]);
 440 }
 441
 442 static void spl_dram_init(void)
 443 {
 444         if (is_mx6solo()) {
 445                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 446                 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
 447         } else if (is_mx6dl()) {
 448                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 449                 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
 450         } else if (is_mx6dq()) {
 451                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 452                 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
 453         }
 454
 455         udelay(100);
 456 }
 457
 458 void board_init_f(ulong dummy)
 459 {
 460         ccgr_init();
 461
 462         /* setup AIPS and disable watchdog */
 463         arch_cpu_init();
 464
 465         gpr_init();
 466
 467         /* iomux */
 468         board_early_init_f();
 469
 470         /* setup GP timer */
 471         timer_init();
 472
 473         /* UART clocks enabled and gd valid - init serial console */
 474         preloader_console_init();
 475
 476         /* DDR initialization */
 477         spl_dram_init();
 478
 479         /* Clear the BSS. */
 480         memset(__bss_start, 0, __bss_end - __bss_start);
 481
 482         /* load/boot image from boot device */
 483         board_init_r(NULL, 0);
 484 }
 485 #endif