board/engicam/icorem6_rqs/icorem6_rqs.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10
  11 #include <asm/io.h>
  12 #include <asm/gpio.h>
  13 #include <linux/sizes.h>
  14
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/iomux.h>
  18 #include <asm/arch/mx6-pins.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/imx-common/iomux-v3.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  25         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  26         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  27
  28 static iomux_v3_cfg_t const uart4_pads[] = {
  29         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  30         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  31 };
  32
  33 int board_early_init_f(void)
  34 {
  35         SETUP_IOMUX_PADS(uart4_pads);
  36
  37         return 0;
  38 }
  39
  40 int board_init(void)
  41 {
  42         /* Address of boot parameters */
  43         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  44
  45         return 0;
  46 }
  47
  48 int board_late_init(void)
  49 {
  50         switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
  51                         IMX6_BMODE_SHIFT) {
  52         case IMX6_BMODE_SD:
  53         case IMX6_BMODE_ESD:
  54         case IMX6_BMODE_MMC:
  55         case IMX6_BMODE_EMMC:
  56                 setenv("modeboot", "mmcboot");
  57                 break;
  58         default:
  59                 setenv("modeboot", "");
  60                 break;
  61         }
  62
  63         return 0;
  64 }
  65
  66 int dram_init(void)
  67 {
  68         gd->ram_size = imx_ddr_size();
  69
  70         return 0;
  71 }
  72
  73 #ifdef CONFIG_SPL_BUILD
  74 #include <libfdt.h>
  75 #include <spl.h>
  76
  77 #include <asm/arch/crm_regs.h>
  78 #include <asm/arch/mx6-ddr.h>
  79
  80 /* MMC board initialization is needed till adding DM support in SPL */
  81 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
  82 #include <mmc.h>
  83 #include <fsl_esdhc.h>
  84
  85 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  86         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_HIGH |               \
  87         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  88
  89 static iomux_v3_cfg_t const usdhc3_pads[] = {
  90         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  91         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  92         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  93         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  94         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  95         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  96 };
  97
  98 static iomux_v3_cfg_t const usdhc4_pads[] = {
  99         IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 100         IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 101         IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 102         IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 103         IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 104         IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 105         IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 106         IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 107         IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 108         IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 109 };
 110
 111 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 112         {USDHC3_BASE_ADDR, 1, 4},
 113         {USDHC4_BASE_ADDR, 1, 8},
 114 };
 115
 116 int board_mmc_getcd(struct mmc *mmc)
 117 {
 118         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 119         int ret = 0;
 120
 121         switch (cfg->esdhc_base) {
 122         case USDHC3_BASE_ADDR:
 123         case USDHC4_BASE_ADDR:
 124                 ret = 1;
 125                 break;
 126         }
 127
 128         return ret;
 129 }
 130
 131 int board_mmc_init(bd_t *bis)
 132 {
 133         int i, ret;
 134
 135         /*
 136         * According to the board_mmc_init() the following map is done:
 137         * (U-boot device node)    (Physical Port)
 138         * mmc0                  USDHC3
 139         * mmc1                  USDHC4
 140         */
 141         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 142                 switch (i) {
 143                 case 0:
 144                         SETUP_IOMUX_PADS(usdhc3_pads);
 145                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 146                         break;
 147                 case 1:
 148                         SETUP_IOMUX_PADS(usdhc4_pads);
 149                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 150                         break;
 151                 default:
 152                         printf("Warning - USDHC%d controller not supporting\n",
 153                                i + 1);
 154                         return 0;
 155                 }
 156
 157                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 158                 if (ret) {
 159                         printf("Warning: failed to initialize mmc dev %d\n", i);
 160                         return ret;
 161                 }
 162         }
 163
 164         return 0;
 165 }
 166
 167 #ifdef CONFIG_ENV_IS_IN_MMC
 168 void board_boot_order(u32 *spl_boot_list)
 169 {
 170         u32 bmode = imx6_src_get_boot_mode();
 171         u8 boot_dev = BOOT_DEVICE_MMC1;
 172
 173         switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
 174         case IMX6_BMODE_SD:
 175         case IMX6_BMODE_ESD:
 176                 /* SD/eSD - BOOT_DEVICE_MMC1 */
 177                 break;
 178         case IMX6_BMODE_MMC:
 179         case IMX6_BMODE_EMMC:
 180                 /* MMC/eMMC */
 181                 boot_dev = BOOT_DEVICE_MMC2;
 182                 break;
 183         default:
 184                 /* Default - BOOT_DEVICE_MMC1 */
 185                 printf("Wrong board boot order\n");
 186                 break;
 187         }
 188
 189         spl_boot_list[0] = boot_dev;
 190 }
 191 #endif
 192 #endif
 193
 194 /*
 195  * Driving strength:
 196  *   0x30 == 40 Ohm
 197  *   0x28 == 48 Ohm
 198  */
 199
 200 #define IMX6DQ_DRIVE_STRENGTH           0x30
 201 #define IMX6SDL_DRIVE_STRENGTH          0x28
 202
 203 /* configure MX6Q/DUAL mmdc DDR io registers */
 204 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 205         .dram_sdqs0 = 0x28,
 206         .dram_sdqs1 = 0x28,
 207         .dram_sdqs2 = 0x28,
 208         .dram_sdqs3 = 0x28,
 209         .dram_sdqs4 = 0x28,
 210         .dram_sdqs5 = 0x28,
 211         .dram_sdqs6 = 0x28,
 212         .dram_sdqs7 = 0x28,
 213         .dram_dqm0 = 0x28,
 214         .dram_dqm1 = 0x28,
 215         .dram_dqm2 = 0x28,
 216         .dram_dqm3 = 0x28,
 217         .dram_dqm4 = 0x28,
 218         .dram_dqm5 = 0x28,
 219         .dram_dqm6 = 0x28,
 220         .dram_dqm7 = 0x28,
 221         .dram_cas = 0x30,
 222         .dram_ras = 0x30,
 223         .dram_sdclk_0 = 0x30,
 224         .dram_sdclk_1 = 0x30,
 225         .dram_reset = 0x30,
 226         .dram_sdcke0 = 0x3000,
 227         .dram_sdcke1 = 0x3000,
 228         .dram_sdba2 = 0x00000000,
 229         .dram_sdodt0 = 0x30,
 230         .dram_sdodt1 = 0x30,
 231 };
 232
 233 /* configure MX6Q/DUAL mmdc GRP io registers */
 234 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 235         .grp_b0ds = 0x30,
 236         .grp_b1ds = 0x30,
 237         .grp_b2ds = 0x30,
 238         .grp_b3ds = 0x30,
 239         .grp_b4ds = 0x30,
 240         .grp_b5ds = 0x30,
 241         .grp_b6ds = 0x30,
 242         .grp_b7ds = 0x30,
 243         .grp_addds = 0x30,
 244         .grp_ddrmode_ctl = 0x00020000,
 245         .grp_ddrpke = 0x00000000,
 246         .grp_ddrmode = 0x00020000,
 247         .grp_ctlds = 0x30,
 248         .grp_ddr_type = 0x000c0000,
 249 };
 250
 251 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 252 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 253         .dram_sdclk_0 = 0x30,
 254         .dram_sdclk_1 = 0x30,
 255         .dram_cas = 0x30,
 256         .dram_ras = 0x30,
 257         .dram_reset = 0x30,
 258         .dram_sdcke0 = 0x30,
 259         .dram_sdcke1 = 0x30,
 260         .dram_sdba2 = 0x00000000,
 261         .dram_sdodt0 = 0x30,
 262         .dram_sdodt1 = 0x30,
 263         .dram_sdqs0 = 0x28,
 264         .dram_sdqs1 = 0x28,
 265         .dram_sdqs2 = 0x28,
 266         .dram_sdqs3 = 0x28,
 267         .dram_sdqs4 = 0x28,
 268         .dram_sdqs5 = 0x28,
 269         .dram_sdqs6 = 0x28,
 270         .dram_sdqs7 = 0x28,
 271         .dram_dqm0 = 0x28,
 272         .dram_dqm1 = 0x28,
 273         .dram_dqm2 = 0x28,
 274         .dram_dqm3 = 0x28,
 275         .dram_dqm4 = 0x28,
 276         .dram_dqm5 = 0x28,
 277         .dram_dqm6 = 0x28,
 278         .dram_dqm7 = 0x28,
 279 };
 280
 281 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 282 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 283         .grp_ddr_type = 0x000c0000,
 284         .grp_ddrmode_ctl = 0x00020000,
 285         .grp_ddrpke = 0x00000000,
 286         .grp_addds = 0x30,
 287         .grp_ctlds = 0x30,
 288         .grp_ddrmode = 0x00020000,
 289         .grp_b0ds = 0x28,
 290         .grp_b1ds = 0x28,
 291         .grp_b2ds = 0x28,
 292         .grp_b3ds = 0x28,
 293         .grp_b4ds = 0x28,
 294         .grp_b5ds = 0x28,
 295         .grp_b6ds = 0x28,
 296         .grp_b7ds = 0x28,
 297 };
 298
 299 /* mt41j256 */
 300 static struct mx6_ddr3_cfg mt41j256 = {
 301         .mem_speed = 1066,
 302         .density = 2,
 303         .width = 16,
 304         .banks = 8,
 305         .rowaddr = 13,
 306         .coladdr = 10,
 307         .pagesz = 2,
 308         .trcd = 1375,
 309         .trcmin = 4875,
 310         .trasmin = 3500,
 311         .SRT = 0,
 312 };
 313
 314 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
 315         .p0_mpwldectrl0 = 0x000E0009,
 316         .p0_mpwldectrl1 = 0x0018000E,
 317         .p1_mpwldectrl0 = 0x00000007,
 318         .p1_mpwldectrl1 = 0x00000000,
 319         .p0_mpdgctrl0 = 0x43280334,
 320         .p0_mpdgctrl1 = 0x031C0314,
 321         .p1_mpdgctrl0 = 0x4318031C,
 322         .p1_mpdgctrl1 = 0x030C0258,
 323         .p0_mprddlctl = 0x3E343A40,
 324         .p1_mprddlctl = 0x383C3844,
 325         .p0_mpwrdlctl = 0x40404440,
 326         .p1_mpwrdlctl = 0x4C3E4446,
 327 };
 328
 329 /* DDR 64bit */
 330 static struct mx6_ddr_sysinfo mem_q = {
 331         .ddr_type       = DDR_TYPE_DDR3,
 332         .dsize          = 2,
 333         .cs1_mirror     = 0,
 334         /* config for full 4GB range so that get_mem_size() works */
 335         .cs_density     = 32,
 336         .ncs            = 1,
 337         .bi_on          = 1,
 338         .rtt_nom        = 2,
 339         .rtt_wr         = 2,
 340         .ralat          = 5,
 341         .walat          = 0,
 342         .mif3_mode      = 3,
 343         .rst_to_cke     = 0x23,
 344         .sde_to_rst     = 0x10,
 345 };
 346
 347 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
 348         .p0_mpwldectrl0 = 0x001F0024,
 349         .p0_mpwldectrl1 = 0x00110018,
 350         .p1_mpwldectrl0 = 0x001F0024,
 351         .p1_mpwldectrl1 = 0x00110018,
 352         .p0_mpdgctrl0 = 0x4230022C,
 353         .p0_mpdgctrl1 = 0x02180220,
 354         .p1_mpdgctrl0 = 0x42440248,
 355         .p1_mpdgctrl1 = 0x02300238,
 356         .p0_mprddlctl = 0x44444A48,
 357         .p1_mprddlctl = 0x46484A42,
 358         .p0_mpwrdlctl = 0x38383234,
 359         .p1_mpwrdlctl = 0x3C34362E,
 360 };
 361
 362 /* DDR 64bit 1GB */
 363 static struct mx6_ddr_sysinfo mem_dl = {
 364         .dsize          = 2,
 365         .cs1_mirror     = 0,
 366         /* config for full 4GB range so that get_mem_size() works */
 367         .cs_density     = 32,
 368         .ncs            = 1,
 369         .bi_on          = 1,
 370         .rtt_nom        = 1,
 371         .rtt_wr         = 1,
 372         .ralat          = 5,
 373         .walat          = 0,
 374         .mif3_mode      = 3,
 375         .rst_to_cke     = 0x23,
 376         .sde_to_rst     = 0x10,
 377 };
 378
 379 /* DDR 32bit 512MB */
 380 static struct mx6_ddr_sysinfo mem_s = {
 381         .dsize          = 1,
 382         .cs1_mirror     = 0,
 383         /* config for full 4GB range so that get_mem_size() works */
 384         .cs_density     = 32,
 385         .ncs            = 1,
 386         .bi_on          = 1,
 387         .rtt_nom        = 1,
 388         .rtt_wr         = 1,
 389         .ralat          = 5,
 390         .walat          = 0,
 391         .mif3_mode      = 3,
 392         .rst_to_cke     = 0x23,
 393         .sde_to_rst     = 0x10,
 394 };
 395
 396 static void ccgr_init(void)
 397 {
 398         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 399
 400         writel(0x00003F3F, &ccm->CCGR0);
 401         writel(0x0030FC00, &ccm->CCGR1);
 402         writel(0x000FC000, &ccm->CCGR2);
 403         writel(0x3F300000, &ccm->CCGR3);
 404         writel(0xFF00F300, &ccm->CCGR4);
 405         writel(0x0F0000C3, &ccm->CCGR5);
 406         writel(0x000003CC, &ccm->CCGR6);
 407 }
 408
 409 static void gpr_init(void)
 410 {
 411         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 412
 413         /* enable AXI cache for VDOA/VPU/IPU */
 414         writel(0xF00000CF, &iomux->gpr[4]);
 415         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 416         writel(0x007F007F, &iomux->gpr[6]);
 417         writel(0x007F007F, &iomux->gpr[7]);
 418 }
 419
 420 static void spl_dram_init(void)
 421 {
 422         if (is_mx6solo()) {
 423                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 424                 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
 425         } else if (is_mx6dl()) {
 426                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 427                 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
 428         } else if (is_mx6dq()) {
 429                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 430                 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
 431         }
 432
 433         udelay(100);
 434 }
 435
 436 void board_init_f(ulong dummy)
 437 {
 438         ccgr_init();
 439
 440         /* setup AIPS and disable watchdog */
 441         arch_cpu_init();
 442
 443         gpr_init();
 444
 445         /* iomux */
 446         board_early_init_f();
 447
 448         /* setup GP timer */
 449         timer_init();
 450
 451         /* UART clocks enabled and gd valid - init serial console */
 452         preloader_console_init();
 453
 454         /* DDR initialization */
 455         spl_dram_init();
 456
 457         /* Clear the BSS. */
 458         memset(__bss_start, 0, __bss_end - __bss_start);
 459
 460         /* load/boot image from boot device */
 461         board_init_r(NULL, 0);
 462 }
 463 #endif