board/engicam/icorem6_rqs/icorem6_rqs.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <mmc.h>
  11
  12 #include <asm/io.h>
  13 #include <asm/gpio.h>
  14 #include <linux/sizes.h>
  15
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/iomux.h>
  19 #include <asm/arch/mx6-pins.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/imx-common/iomux-v3.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  26         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  27         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  28
  29 static iomux_v3_cfg_t const uart4_pads[] = {
  30         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  31         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  32 };
  33
  34 int board_early_init_f(void)
  35 {
  36         SETUP_IOMUX_PADS(uart4_pads);
  37
  38         return 0;
  39 }
  40
  41 int board_init(void)
  42 {
  43         /* Address of boot parameters */
  44         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  45
  46         return 0;
  47 }
  48
  49 #ifdef CONFIG_ENV_IS_IN_MMC
  50 int board_mmc_get_env_dev(int devno)
  51 {
  52         /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
  53         return (devno == 3) ? 1 : 0;
  54 }
  55
  56 static void mmc_late_init(void)
  57 {
  58         char cmd[32];
  59         char mmcblk[32];
  60         u32 dev_no = mmc_get_env_dev();
  61
  62         setenv_ulong("mmcdev", dev_no);
  63
  64         /* Set mmcblk env */
  65         sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
  66         setenv("mmcroot", mmcblk);
  67
  68         sprintf(cmd, "mmc dev %d", dev_no);
  69         run_command(cmd, 0);
  70 }
  71 #endif
  72
  73 int board_late_init(void)
  74 {
  75         switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
  76                         IMX6_BMODE_SHIFT) {
  77         case IMX6_BMODE_SD:
  78         case IMX6_BMODE_ESD:
  79         case IMX6_BMODE_MMC:
  80         case IMX6_BMODE_EMMC:
  81 #ifdef CONFIG_ENV_IS_IN_MMC
  82                 mmc_late_init();
  83 #endif
  84                 setenv("modeboot", "mmcboot");
  85                 break;
  86         default:
  87                 setenv("modeboot", "");
  88                 break;
  89         }
  90
  91         if (is_mx6dq())
  92                 setenv("fdt_file", "imx6q-icore-rqs.dtb");
  93         else if(is_mx6dl() || is_mx6solo())
  94                 setenv("fdt_file", "imx6dl-icore-rqs.dtb");
  95
  96         return 0;
  97 }
  98
  99 int dram_init(void)
 100 {
 101         gd->ram_size = imx_ddr_size();
 102
 103         return 0;
 104 }
 105
 106 #ifdef CONFIG_SPL_BUILD
 107 #include <libfdt.h>
 108 #include <spl.h>
 109
 110 #include <asm/arch/crm_regs.h>
 111 #include <asm/arch/mx6-ddr.h>
 112
 113 /* MMC board initialization is needed till adding DM support in SPL */
 114 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
 115 #include <mmc.h>
 116 #include <fsl_esdhc.h>
 117
 118 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 119         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_HIGH |               \
 120         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 121
 122 static iomux_v3_cfg_t const usdhc3_pads[] = {
 123         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 124         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 125         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 126         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 127         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 128         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 129 };
 130
 131 static iomux_v3_cfg_t const usdhc4_pads[] = {
 132         IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 133         IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 134         IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 135         IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 136         IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 137         IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 138         IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 139         IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 140         IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 141         IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 142 };
 143
 144 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 145         {USDHC3_BASE_ADDR, 1, 4},
 146         {USDHC4_BASE_ADDR, 1, 8},
 147 };
 148
 149 int board_mmc_getcd(struct mmc *mmc)
 150 {
 151         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 152         int ret = 0;
 153
 154         switch (cfg->esdhc_base) {
 155         case USDHC3_BASE_ADDR:
 156         case USDHC4_BASE_ADDR:
 157                 ret = 1;
 158                 break;
 159         }
 160
 161         return ret;
 162 }
 163
 164 int board_mmc_init(bd_t *bis)
 165 {
 166         int i, ret;
 167
 168         /*
 169         * According to the board_mmc_init() the following map is done:
 170         * (U-boot device node)    (Physical Port)
 171         * mmc0                  USDHC3
 172         * mmc1                  USDHC4
 173         */
 174         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 175                 switch (i) {
 176                 case 0:
 177                         SETUP_IOMUX_PADS(usdhc3_pads);
 178                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 179                         break;
 180                 case 1:
 181                         SETUP_IOMUX_PADS(usdhc4_pads);
 182                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 183                         break;
 184                 default:
 185                         printf("Warning - USDHC%d controller not supporting\n",
 186                                i + 1);
 187                         return 0;
 188                 }
 189
 190                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 191                 if (ret) {
 192                         printf("Warning: failed to initialize mmc dev %d\n", i);
 193                         return ret;
 194                 }
 195         }
 196
 197         return 0;
 198 }
 199
 200 #ifdef CONFIG_ENV_IS_IN_MMC
 201 void board_boot_order(u32 *spl_boot_list)
 202 {
 203         u32 bmode = imx6_src_get_boot_mode();
 204         u8 boot_dev = BOOT_DEVICE_MMC1;
 205
 206         switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
 207         case IMX6_BMODE_SD:
 208         case IMX6_BMODE_ESD:
 209                 /* SD/eSD - BOOT_DEVICE_MMC1 */
 210                 break;
 211         case IMX6_BMODE_MMC:
 212         case IMX6_BMODE_EMMC:
 213                 /* MMC/eMMC */
 214                 boot_dev = BOOT_DEVICE_MMC2;
 215                 break;
 216         default:
 217                 /* Default - BOOT_DEVICE_MMC1 */
 218                 printf("Wrong board boot order\n");
 219                 break;
 220         }
 221
 222         spl_boot_list[0] = boot_dev;
 223 }
 224 #endif
 225 #endif
 226
 227 /*
 228  * Driving strength:
 229  *   0x30 == 40 Ohm
 230  *   0x28 == 48 Ohm
 231  */
 232
 233 #define IMX6DQ_DRIVE_STRENGTH           0x30
 234 #define IMX6SDL_DRIVE_STRENGTH          0x28
 235
 236 /* configure MX6Q/DUAL mmdc DDR io registers */
 237 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 238         .dram_sdqs0 = 0x28,
 239         .dram_sdqs1 = 0x28,
 240         .dram_sdqs2 = 0x28,
 241         .dram_sdqs3 = 0x28,
 242         .dram_sdqs4 = 0x28,
 243         .dram_sdqs5 = 0x28,
 244         .dram_sdqs6 = 0x28,
 245         .dram_sdqs7 = 0x28,
 246         .dram_dqm0 = 0x28,
 247         .dram_dqm1 = 0x28,
 248         .dram_dqm2 = 0x28,
 249         .dram_dqm3 = 0x28,
 250         .dram_dqm4 = 0x28,
 251         .dram_dqm5 = 0x28,
 252         .dram_dqm6 = 0x28,
 253         .dram_dqm7 = 0x28,
 254         .dram_cas = 0x30,
 255         .dram_ras = 0x30,
 256         .dram_sdclk_0 = 0x30,
 257         .dram_sdclk_1 = 0x30,
 258         .dram_reset = 0x30,
 259         .dram_sdcke0 = 0x3000,
 260         .dram_sdcke1 = 0x3000,
 261         .dram_sdba2 = 0x00000000,
 262         .dram_sdodt0 = 0x30,
 263         .dram_sdodt1 = 0x30,
 264 };
 265
 266 /* configure MX6Q/DUAL mmdc GRP io registers */
 267 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 268         .grp_b0ds = 0x30,
 269         .grp_b1ds = 0x30,
 270         .grp_b2ds = 0x30,
 271         .grp_b3ds = 0x30,
 272         .grp_b4ds = 0x30,
 273         .grp_b5ds = 0x30,
 274         .grp_b6ds = 0x30,
 275         .grp_b7ds = 0x30,
 276         .grp_addds = 0x30,
 277         .grp_ddrmode_ctl = 0x00020000,
 278         .grp_ddrpke = 0x00000000,
 279         .grp_ddrmode = 0x00020000,
 280         .grp_ctlds = 0x30,
 281         .grp_ddr_type = 0x000c0000,
 282 };
 283
 284 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 285 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 286         .dram_sdclk_0 = 0x30,
 287         .dram_sdclk_1 = 0x30,
 288         .dram_cas = 0x30,
 289         .dram_ras = 0x30,
 290         .dram_reset = 0x30,
 291         .dram_sdcke0 = 0x30,
 292         .dram_sdcke1 = 0x30,
 293         .dram_sdba2 = 0x00000000,
 294         .dram_sdodt0 = 0x30,
 295         .dram_sdodt1 = 0x30,
 296         .dram_sdqs0 = 0x28,
 297         .dram_sdqs1 = 0x28,
 298         .dram_sdqs2 = 0x28,
 299         .dram_sdqs3 = 0x28,
 300         .dram_sdqs4 = 0x28,
 301         .dram_sdqs5 = 0x28,
 302         .dram_sdqs6 = 0x28,
 303         .dram_sdqs7 = 0x28,
 304         .dram_dqm0 = 0x28,
 305         .dram_dqm1 = 0x28,
 306         .dram_dqm2 = 0x28,
 307         .dram_dqm3 = 0x28,
 308         .dram_dqm4 = 0x28,
 309         .dram_dqm5 = 0x28,
 310         .dram_dqm6 = 0x28,
 311         .dram_dqm7 = 0x28,
 312 };
 313
 314 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 315 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 316         .grp_ddr_type = 0x000c0000,
 317         .grp_ddrmode_ctl = 0x00020000,
 318         .grp_ddrpke = 0x00000000,
 319         .grp_addds = 0x30,
 320         .grp_ctlds = 0x30,
 321         .grp_ddrmode = 0x00020000,
 322         .grp_b0ds = 0x28,
 323         .grp_b1ds = 0x28,
 324         .grp_b2ds = 0x28,
 325         .grp_b3ds = 0x28,
 326         .grp_b4ds = 0x28,
 327         .grp_b5ds = 0x28,
 328         .grp_b6ds = 0x28,
 329         .grp_b7ds = 0x28,
 330 };
 331
 332 /* mt41j256 */
 333 static struct mx6_ddr3_cfg mt41j256 = {
 334         .mem_speed = 1066,
 335         .density = 2,
 336         .width = 16,
 337         .banks = 8,
 338         .rowaddr = 13,
 339         .coladdr = 10,
 340         .pagesz = 2,
 341         .trcd = 1375,
 342         .trcmin = 4875,
 343         .trasmin = 3500,
 344         .SRT = 0,
 345 };
 346
 347 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
 348         .p0_mpwldectrl0 = 0x000E0009,
 349         .p0_mpwldectrl1 = 0x0018000E,
 350         .p1_mpwldectrl0 = 0x00000007,
 351         .p1_mpwldectrl1 = 0x00000000,
 352         .p0_mpdgctrl0 = 0x43280334,
 353         .p0_mpdgctrl1 = 0x031C0314,
 354         .p1_mpdgctrl0 = 0x4318031C,
 355         .p1_mpdgctrl1 = 0x030C0258,
 356         .p0_mprddlctl = 0x3E343A40,
 357         .p1_mprddlctl = 0x383C3844,
 358         .p0_mpwrdlctl = 0x40404440,
 359         .p1_mpwrdlctl = 0x4C3E4446,
 360 };
 361
 362 /* DDR 64bit */
 363 static struct mx6_ddr_sysinfo mem_q = {
 364         .ddr_type       = DDR_TYPE_DDR3,
 365         .dsize          = 2,
 366         .cs1_mirror     = 0,
 367         /* config for full 4GB range so that get_mem_size() works */
 368         .cs_density     = 32,
 369         .ncs            = 1,
 370         .bi_on          = 1,
 371         .rtt_nom        = 2,
 372         .rtt_wr         = 2,
 373         .ralat          = 5,
 374         .walat          = 0,
 375         .mif3_mode      = 3,
 376         .rst_to_cke     = 0x23,
 377         .sde_to_rst     = 0x10,
 378 };
 379
 380 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
 381         .p0_mpwldectrl0 = 0x001F0024,
 382         .p0_mpwldectrl1 = 0x00110018,
 383         .p1_mpwldectrl0 = 0x001F0024,
 384         .p1_mpwldectrl1 = 0x00110018,
 385         .p0_mpdgctrl0 = 0x4230022C,
 386         .p0_mpdgctrl1 = 0x02180220,
 387         .p1_mpdgctrl0 = 0x42440248,
 388         .p1_mpdgctrl1 = 0x02300238,
 389         .p0_mprddlctl = 0x44444A48,
 390         .p1_mprddlctl = 0x46484A42,
 391         .p0_mpwrdlctl = 0x38383234,
 392         .p1_mpwrdlctl = 0x3C34362E,
 393 };
 394
 395 /* DDR 64bit 1GB */
 396 static struct mx6_ddr_sysinfo mem_dl = {
 397         .dsize          = 2,
 398         .cs1_mirror     = 0,
 399         /* config for full 4GB range so that get_mem_size() works */
 400         .cs_density     = 32,
 401         .ncs            = 1,
 402         .bi_on          = 1,
 403         .rtt_nom        = 1,
 404         .rtt_wr         = 1,
 405         .ralat          = 5,
 406         .walat          = 0,
 407         .mif3_mode      = 3,
 408         .rst_to_cke     = 0x23,
 409         .sde_to_rst     = 0x10,
 410 };
 411
 412 /* DDR 32bit 512MB */
 413 static struct mx6_ddr_sysinfo mem_s = {
 414         .dsize          = 1,
 415         .cs1_mirror     = 0,
 416         /* config for full 4GB range so that get_mem_size() works */
 417         .cs_density     = 32,
 418         .ncs            = 1,
 419         .bi_on          = 1,
 420         .rtt_nom        = 1,
 421         .rtt_wr         = 1,
 422         .ralat          = 5,
 423         .walat          = 0,
 424         .mif3_mode      = 3,
 425         .rst_to_cke     = 0x23,
 426         .sde_to_rst     = 0x10,
 427 };
 428
 429 static void ccgr_init(void)
 430 {
 431         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 432
 433         writel(0x00003F3F, &ccm->CCGR0);
 434         writel(0x0030FC00, &ccm->CCGR1);
 435         writel(0x000FC000, &ccm->CCGR2);
 436         writel(0x3F300000, &ccm->CCGR3);
 437         writel(0xFF00F300, &ccm->CCGR4);
 438         writel(0x0F0000C3, &ccm->CCGR5);
 439         writel(0x000003CC, &ccm->CCGR6);
 440 }
 441
 442 static void gpr_init(void)
 443 {
 444         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 445
 446         /* enable AXI cache for VDOA/VPU/IPU */
 447         writel(0xF00000CF, &iomux->gpr[4]);
 448         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 449         writel(0x007F007F, &iomux->gpr[6]);
 450         writel(0x007F007F, &iomux->gpr[7]);
 451 }
 452
 453 static void spl_dram_init(void)
 454 {
 455         if (is_mx6solo()) {
 456                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 457                 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
 458         } else if (is_mx6dl()) {
 459                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 460                 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
 461         } else if (is_mx6dq()) {
 462                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 463                 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
 464         }
 465
 466         udelay(100);
 467 }
 468
 469 void board_init_f(ulong dummy)
 470 {
 471         ccgr_init();
 472
 473         /* setup AIPS and disable watchdog */
 474         arch_cpu_init();
 475
 476         gpr_init();
 477
 478         /* iomux */
 479         board_early_init_f();
 480
 481         /* setup GP timer */
 482         timer_init();
 483
 484         /* UART clocks enabled and gd valid - init serial console */
 485         preloader_console_init();
 486
 487         /* DDR initialization */
 488         spl_dram_init();
 489
 490         /* Clear the BSS. */
 491         memset(__bss_start, 0, __bss_end - __bss_start);
 492
 493         /* load/boot image from boot device */
 494         board_init_r(NULL, 0);
 495 }
 496 #endif