2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/sizes.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/mx6-pins.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/imx-common/iomux-v3.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
26 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
27 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
29 static iomux_v3_cfg_t const uart4_pads[] = {
30 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
31 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
34 int board_early_init_f(void)
36 SETUP_IOMUX_PADS(uart4_pads);
43 /* Address of boot parameters */
44 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
49 #ifdef CONFIG_ENV_IS_IN_MMC
50 int board_mmc_get_env_dev(int devno)
52 /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
53 return (devno == 3) ? 1 : 0;
56 static void mmc_late_init(void)
60 u32 dev_no = mmc_get_env_dev();
62 setenv_ulong("mmcdev", dev_no);
65 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
66 setenv("mmcroot", mmcblk);
68 sprintf(cmd, "mmc dev %d", dev_no);
73 int board_late_init(void)
75 switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
81 #ifdef CONFIG_ENV_IS_IN_MMC
84 setenv("modeboot", "mmcboot");
87 setenv("modeboot", "");
92 setenv("fdt_file", "imx6q-icore-rqs.dtb");
93 else if(is_mx6dl() || is_mx6solo())
94 setenv("fdt_file", "imx6dl-icore-rqs.dtb");
101 gd->ram_size = imx_ddr_size();
106 #ifdef CONFIG_SPL_BUILD
110 #include <asm/arch/crm_regs.h>
111 #include <asm/arch/mx6-ddr.h>
113 /* MMC board initialization is needed till adding DM support in SPL */
114 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
116 #include <fsl_esdhc.h>
118 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
119 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
120 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
122 static iomux_v3_cfg_t const usdhc3_pads[] = {
123 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
124 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
125 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
126 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
127 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
128 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
131 static iomux_v3_cfg_t const usdhc4_pads[] = {
132 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
133 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
134 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
135 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
136 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
137 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
138 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
139 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
140 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
141 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
144 struct fsl_esdhc_cfg usdhc_cfg[2] = {
145 {USDHC3_BASE_ADDR, 1, 4},
146 {USDHC4_BASE_ADDR, 1, 8},
149 int board_mmc_getcd(struct mmc *mmc)
151 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
154 switch (cfg->esdhc_base) {
155 case USDHC3_BASE_ADDR:
156 case USDHC4_BASE_ADDR:
164 int board_mmc_init(bd_t *bis)
169 * According to the board_mmc_init() the following map is done:
170 * (U-boot device node) (Physical Port)
174 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
177 SETUP_IOMUX_PADS(usdhc3_pads);
178 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
181 SETUP_IOMUX_PADS(usdhc4_pads);
182 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
185 printf("Warning - USDHC%d controller not supporting\n",
190 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
192 printf("Warning: failed to initialize mmc dev %d\n", i);
200 #ifdef CONFIG_ENV_IS_IN_MMC
201 void board_boot_order(u32 *spl_boot_list)
203 u32 bmode = imx6_src_get_boot_mode();
204 u8 boot_dev = BOOT_DEVICE_MMC1;
206 switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
209 /* SD/eSD - BOOT_DEVICE_MMC1 */
212 case IMX6_BMODE_EMMC:
214 boot_dev = BOOT_DEVICE_MMC2;
217 /* Default - BOOT_DEVICE_MMC1 */
218 printf("Wrong board boot order\n");
222 spl_boot_list[0] = boot_dev;
233 #define IMX6DQ_DRIVE_STRENGTH 0x30
234 #define IMX6SDL_DRIVE_STRENGTH 0x28
236 /* configure MX6Q/DUAL mmdc DDR io registers */
237 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
256 .dram_sdclk_0 = 0x30,
257 .dram_sdclk_1 = 0x30,
259 .dram_sdcke0 = 0x3000,
260 .dram_sdcke1 = 0x3000,
261 .dram_sdba2 = 0x00000000,
266 /* configure MX6Q/DUAL mmdc GRP io registers */
267 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
277 .grp_ddrmode_ctl = 0x00020000,
278 .grp_ddrpke = 0x00000000,
279 .grp_ddrmode = 0x00020000,
281 .grp_ddr_type = 0x000c0000,
284 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
285 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
286 .dram_sdclk_0 = 0x30,
287 .dram_sdclk_1 = 0x30,
293 .dram_sdba2 = 0x00000000,
314 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
315 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
316 .grp_ddr_type = 0x000c0000,
317 .grp_ddrmode_ctl = 0x00020000,
318 .grp_ddrpke = 0x00000000,
321 .grp_ddrmode = 0x00020000,
333 static struct mx6_ddr3_cfg mt41j256 = {
347 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
348 .p0_mpwldectrl0 = 0x000E0009,
349 .p0_mpwldectrl1 = 0x0018000E,
350 .p1_mpwldectrl0 = 0x00000007,
351 .p1_mpwldectrl1 = 0x00000000,
352 .p0_mpdgctrl0 = 0x43280334,
353 .p0_mpdgctrl1 = 0x031C0314,
354 .p1_mpdgctrl0 = 0x4318031C,
355 .p1_mpdgctrl1 = 0x030C0258,
356 .p0_mprddlctl = 0x3E343A40,
357 .p1_mprddlctl = 0x383C3844,
358 .p0_mpwrdlctl = 0x40404440,
359 .p1_mpwrdlctl = 0x4C3E4446,
363 static struct mx6_ddr_sysinfo mem_q = {
364 .ddr_type = DDR_TYPE_DDR3,
367 /* config for full 4GB range so that get_mem_size() works */
380 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
381 .p0_mpwldectrl0 = 0x001F0024,
382 .p0_mpwldectrl1 = 0x00110018,
383 .p1_mpwldectrl0 = 0x001F0024,
384 .p1_mpwldectrl1 = 0x00110018,
385 .p0_mpdgctrl0 = 0x4230022C,
386 .p0_mpdgctrl1 = 0x02180220,
387 .p1_mpdgctrl0 = 0x42440248,
388 .p1_mpdgctrl1 = 0x02300238,
389 .p0_mprddlctl = 0x44444A48,
390 .p1_mprddlctl = 0x46484A42,
391 .p0_mpwrdlctl = 0x38383234,
392 .p1_mpwrdlctl = 0x3C34362E,
396 static struct mx6_ddr_sysinfo mem_dl = {
399 /* config for full 4GB range so that get_mem_size() works */
412 /* DDR 32bit 512MB */
413 static struct mx6_ddr_sysinfo mem_s = {
416 /* config for full 4GB range so that get_mem_size() works */
429 static void ccgr_init(void)
431 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
433 writel(0x00003F3F, &ccm->CCGR0);
434 writel(0x0030FC00, &ccm->CCGR1);
435 writel(0x000FC000, &ccm->CCGR2);
436 writel(0x3F300000, &ccm->CCGR3);
437 writel(0xFF00F300, &ccm->CCGR4);
438 writel(0x0F0000C3, &ccm->CCGR5);
439 writel(0x000003CC, &ccm->CCGR6);
442 static void gpr_init(void)
444 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
446 /* enable AXI cache for VDOA/VPU/IPU */
447 writel(0xF00000CF, &iomux->gpr[4]);
448 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
449 writel(0x007F007F, &iomux->gpr[6]);
450 writel(0x007F007F, &iomux->gpr[7]);
453 static void spl_dram_init(void)
456 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
457 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
458 } else if (is_mx6dl()) {
459 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
460 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
461 } else if (is_mx6dq()) {
462 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
463 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
469 void board_init_f(ulong dummy)
473 /* setup AIPS and disable watchdog */
479 board_early_init_f();
484 /* UART clocks enabled and gd valid - init serial console */
485 preloader_console_init();
487 /* DDR initialization */
491 memset(__bss_start, 0, __bss_end - __bss_start);
493 /* load/boot image from boot device */
494 board_init_r(NULL, 0);