2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/sizes.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/mx6-pins.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/imx-common/iomux-v3.h>
23 #include "../common/board.h"
25 DECLARE_GLOBAL_DATA_PTR;
27 #ifdef CONFIG_ENV_IS_IN_MMC
28 int board_mmc_get_env_dev(int devno)
30 /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
31 return (devno == 3) ? 1 : 0;
35 int board_late_init(void)
37 switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
43 #ifdef CONFIG_ENV_IS_IN_MMC
46 setenv("modeboot", "mmcboot");
49 setenv("modeboot", "");
54 setenv("fdt_file", "imx6q-icore-rqs.dtb");
55 else if(is_mx6dl() || is_mx6solo())
56 setenv("fdt_file", "imx6dl-icore-rqs.dtb");
61 #ifdef CONFIG_SPL_BUILD
64 /* MMC board initialization is needed till adding DM support in SPL */
65 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
67 #include <fsl_esdhc.h>
69 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
70 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
71 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
73 static iomux_v3_cfg_t const usdhc3_pads[] = {
74 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
75 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
76 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
77 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
78 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
79 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
82 static iomux_v3_cfg_t const usdhc4_pads[] = {
83 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
84 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
85 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
86 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
87 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
88 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
89 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
90 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
91 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
92 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
95 struct fsl_esdhc_cfg usdhc_cfg[2] = {
96 {USDHC3_BASE_ADDR, 1, 4},
97 {USDHC4_BASE_ADDR, 1, 8},
100 int board_mmc_getcd(struct mmc *mmc)
102 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
105 switch (cfg->esdhc_base) {
106 case USDHC3_BASE_ADDR:
107 case USDHC4_BASE_ADDR:
115 int board_mmc_init(bd_t *bis)
120 * According to the board_mmc_init() the following map is done:
121 * (U-boot device node) (Physical Port)
125 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
128 SETUP_IOMUX_PADS(usdhc3_pads);
129 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
132 SETUP_IOMUX_PADS(usdhc4_pads);
133 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
136 printf("Warning - USDHC%d controller not supporting\n",
141 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
143 printf("Warning: failed to initialize mmc dev %d\n", i);
151 #ifdef CONFIG_ENV_IS_IN_MMC
152 void board_boot_order(u32 *spl_boot_list)
154 u32 bmode = imx6_src_get_boot_mode();
155 u8 boot_dev = BOOT_DEVICE_MMC1;
157 switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
160 /* SD/eSD - BOOT_DEVICE_MMC1 */
163 case IMX6_BMODE_EMMC:
165 boot_dev = BOOT_DEVICE_MMC2;
168 /* Default - BOOT_DEVICE_MMC1 */
169 printf("Wrong board boot order\n");
173 spl_boot_list[0] = boot_dev;
178 #ifdef CONFIG_SPL_LOAD_FIT
179 int board_fit_config_name_match(const char *name)
181 if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
183 else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
189 #endif /* CONFIG_SPL_BUILD */