2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/sizes.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/iomux.h>
18 #include <asm/arch/mx6-pins.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/imx-common/iomux-v3.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
25 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
26 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
28 static iomux_v3_cfg_t const uart4_pads[] = {
29 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
30 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
33 int board_early_init_f(void)
35 SETUP_IOMUX_PADS(uart4_pads);
42 /* Address of boot parameters */
43 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
50 gd->ram_size = imx_ddr_size();
55 #ifdef CONFIG_SPL_BUILD
59 #include <asm/arch/crm_regs.h>
60 #include <asm/arch/mx6-ddr.h>
62 /* MMC board initialization is needed till adding DM support in SPL */
63 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
65 #include <fsl_esdhc.h>
67 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
68 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
69 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
71 static iomux_v3_cfg_t const usdhc3_pads[] = {
72 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
73 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
74 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
75 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
76 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
77 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
80 static iomux_v3_cfg_t const usdhc4_pads[] = {
81 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
82 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
83 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
84 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
85 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
86 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
87 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
88 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
89 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
90 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
93 struct fsl_esdhc_cfg usdhc_cfg[2] = {
94 {USDHC3_BASE_ADDR, 1, 4},
95 {USDHC4_BASE_ADDR, 1, 8},
98 int board_mmc_getcd(struct mmc *mmc)
100 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
103 switch (cfg->esdhc_base) {
104 case USDHC3_BASE_ADDR:
105 case USDHC4_BASE_ADDR:
113 int board_mmc_init(bd_t *bis)
118 * According to the board_mmc_init() the following map is done:
119 * (U-boot device node) (Physical Port)
123 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
126 SETUP_IOMUX_PADS(usdhc3_pads);
127 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
130 SETUP_IOMUX_PADS(usdhc4_pads);
131 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
134 printf("Warning - USDHC%d controller not supporting\n",
139 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
141 printf("Warning: failed to initialize mmc dev %d\n", i);
149 #ifdef CONFIG_ENV_IS_IN_MMC
150 void board_boot_order(u32 *spl_boot_list)
152 u32 bmode = imx6_src_get_boot_mode();
153 u8 boot_dev = BOOT_DEVICE_MMC1;
155 switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
158 /* SD/eSD - BOOT_DEVICE_MMC1 */
161 case IMX6_BMODE_EMMC:
163 boot_dev = BOOT_DEVICE_MMC2;
166 /* Default - BOOT_DEVICE_MMC1 */
167 printf("Wrong board boot order\n");
171 spl_boot_list[0] = boot_dev;
182 #define IMX6DQ_DRIVE_STRENGTH 0x30
183 #define IMX6SDL_DRIVE_STRENGTH 0x28
185 /* configure MX6Q/DUAL mmdc DDR io registers */
186 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
205 .dram_sdclk_0 = 0x30,
206 .dram_sdclk_1 = 0x30,
208 .dram_sdcke0 = 0x3000,
209 .dram_sdcke1 = 0x3000,
210 .dram_sdba2 = 0x00000000,
215 /* configure MX6Q/DUAL mmdc GRP io registers */
216 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
226 .grp_ddrmode_ctl = 0x00020000,
227 .grp_ddrpke = 0x00000000,
228 .grp_ddrmode = 0x00020000,
230 .grp_ddr_type = 0x000c0000,
233 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
234 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
235 .dram_sdclk_0 = 0x30,
236 .dram_sdclk_1 = 0x30,
242 .dram_sdba2 = 0x00000000,
263 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
264 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
265 .grp_ddr_type = 0x000c0000,
266 .grp_ddrmode_ctl = 0x00020000,
267 .grp_ddrpke = 0x00000000,
270 .grp_ddrmode = 0x00020000,
282 static struct mx6_ddr3_cfg mt41j256 = {
296 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
297 .p0_mpwldectrl0 = 0x000E0009,
298 .p0_mpwldectrl1 = 0x0018000E,
299 .p1_mpwldectrl0 = 0x00000007,
300 .p1_mpwldectrl1 = 0x00000000,
301 .p0_mpdgctrl0 = 0x43280334,
302 .p0_mpdgctrl1 = 0x031C0314,
303 .p1_mpdgctrl0 = 0x4318031C,
304 .p1_mpdgctrl1 = 0x030C0258,
305 .p0_mprddlctl = 0x3E343A40,
306 .p1_mprddlctl = 0x383C3844,
307 .p0_mpwrdlctl = 0x40404440,
308 .p1_mpwrdlctl = 0x4C3E4446,
312 static struct mx6_ddr_sysinfo mem_q = {
313 .ddr_type = DDR_TYPE_DDR3,
316 /* config for full 4GB range so that get_mem_size() works */
329 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
330 .p0_mpwldectrl0 = 0x001F0024,
331 .p0_mpwldectrl1 = 0x00110018,
332 .p1_mpwldectrl0 = 0x001F0024,
333 .p1_mpwldectrl1 = 0x00110018,
334 .p0_mpdgctrl0 = 0x4230022C,
335 .p0_mpdgctrl1 = 0x02180220,
336 .p1_mpdgctrl0 = 0x42440248,
337 .p1_mpdgctrl1 = 0x02300238,
338 .p0_mprddlctl = 0x44444A48,
339 .p1_mprddlctl = 0x46484A42,
340 .p0_mpwrdlctl = 0x38383234,
341 .p1_mpwrdlctl = 0x3C34362E,
345 static struct mx6_ddr_sysinfo mem_dl = {
348 /* config for full 4GB range so that get_mem_size() works */
361 /* DDR 32bit 512MB */
362 static struct mx6_ddr_sysinfo mem_s = {
365 /* config for full 4GB range so that get_mem_size() works */
378 static void ccgr_init(void)
380 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
382 writel(0x00003F3F, &ccm->CCGR0);
383 writel(0x0030FC00, &ccm->CCGR1);
384 writel(0x000FC000, &ccm->CCGR2);
385 writel(0x3F300000, &ccm->CCGR3);
386 writel(0xFF00F300, &ccm->CCGR4);
387 writel(0x0F0000C3, &ccm->CCGR5);
388 writel(0x000003CC, &ccm->CCGR6);
391 static void gpr_init(void)
393 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
395 /* enable AXI cache for VDOA/VPU/IPU */
396 writel(0xF00000CF, &iomux->gpr[4]);
397 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
398 writel(0x007F007F, &iomux->gpr[6]);
399 writel(0x007F007F, &iomux->gpr[7]);
402 static void spl_dram_init(void)
405 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
406 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
407 } else if (is_mx6dl()) {
408 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
409 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
410 } else if (is_mx6dq()) {
411 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
412 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
418 void board_init_f(ulong dummy)
422 /* setup AIPS and disable watchdog */
428 board_early_init_f();
433 /* UART clocks enabled and gd valid - init serial console */
434 preloader_console_init();
436 /* DDR initialization */
440 memset(__bss_start, 0, __bss_end - __bss_start);
442 /* load/boot image from boot device */
443 board_init_r(NULL, 0);