board/engicam/icorem6/icorem6.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <fsl_esdhc.h>
  11 #include <mmc.h>
  12
  13 #include <asm/io.h>
  14 #include <asm/gpio.h>
  15 #include <linux/sizes.h>
  16
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/iomux.h>
  19 #include <asm/arch/mx6-pins.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/imx-common/iomux-v3.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  26         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  27         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  28
  29 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  30         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  31         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  32
  33 static iomux_v3_cfg_t const uart4_pads[] = {
  34         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  35         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  36 };
  37
  38 static iomux_v3_cfg_t const usdhc1_pads[] = {
  39         IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  40         IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  41         IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  42         IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  43         IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  44         IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  45         IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
  46 };
  47
  48 #ifdef CONFIG_FSL_ESDHC
  49 #define USDHC1_CD_GPIO  IMX_GPIO_NR(1, 1)
  50
  51 struct fsl_esdhc_cfg usdhc_cfg[1] = {
  52         {USDHC1_BASE_ADDR, 0, 4},
  53 };
  54
  55 int board_mmc_getcd(struct mmc *mmc)
  56 {
  57         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  58         int ret = 0;
  59
  60         switch (cfg->esdhc_base) {
  61         case USDHC1_BASE_ADDR:
  62                 ret = !gpio_get_value(USDHC1_CD_GPIO);
  63                 break;
  64         }
  65
  66         return ret;
  67 }
  68
  69 int board_mmc_init(bd_t *bis)
  70 {
  71         int i, ret;
  72
  73         /*
  74         * According to the board_mmc_init() the following map is done:
  75         * (U-boot device node)    (Physical Port)
  76         * mmc0                          USDHC1
  77         */
  78         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  79                 switch (i) {
  80                 case 0:
  81                         SETUP_IOMUX_PADS(usdhc1_pads);
  82                         gpio_direction_input(USDHC1_CD_GPIO);
  83                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  84                         break;
  85                 default:
  86                         printf("Warning - USDHC%d controller not supporting\n",
  87                                i + 1);
  88                         return 0;
  89                 }
  90
  91                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  92                 if (ret) {
  93                         printf("Warning: failed to initialize mmc dev %d\n", i);
  94                         return ret;
  95                 }
  96         }
  97
  98         return 0;
  99 }
 100 #endif
 101
 102 int board_early_init_f(void)
 103 {
 104         SETUP_IOMUX_PADS(uart4_pads);
 105
 106         return 0;
 107 }
 108
 109 int board_init(void)
 110 {
 111         /* Address of boot parameters */
 112         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 113
 114         return 0;
 115 }
 116
 117 int dram_init(void)
 118 {
 119         gd->ram_size = imx_ddr_size();
 120
 121         return 0;
 122 }
 123
 124 #ifdef CONFIG_SPL_BUILD
 125 #include <libfdt.h>
 126 #include <spl.h>
 127
 128 #include <asm/arch/crm_regs.h>
 129 #include <asm/arch/mx6-ddr.h>
 130
 131 /*
 132  * Driving strength:
 133  *   0x30 == 40 Ohm
 134  *   0x28 == 48 Ohm
 135  */
 136
 137 #define IMX6DQ_DRIVE_STRENGTH           0x30
 138 #define IMX6SDL_DRIVE_STRENGTH          0x28
 139
 140 /* configure MX6Q/DUAL mmdc DDR io registers */
 141 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 142         .dram_sdqs0 = 0x28,
 143         .dram_sdqs1 = 0x28,
 144         .dram_sdqs2 = 0x28,
 145         .dram_sdqs3 = 0x28,
 146         .dram_sdqs4 = 0x28,
 147         .dram_sdqs5 = 0x28,
 148         .dram_sdqs6 = 0x28,
 149         .dram_sdqs7 = 0x28,
 150         .dram_dqm0 = 0x28,
 151         .dram_dqm1 = 0x28,
 152         .dram_dqm2 = 0x28,
 153         .dram_dqm3 = 0x28,
 154         .dram_dqm4 = 0x28,
 155         .dram_dqm5 = 0x28,
 156         .dram_dqm6 = 0x28,
 157         .dram_dqm7 = 0x28,
 158         .dram_cas = 0x30,
 159         .dram_ras = 0x30,
 160         .dram_sdclk_0 = 0x30,
 161         .dram_sdclk_1 = 0x30,
 162         .dram_reset = 0x30,
 163         .dram_sdcke0 = 0x3000,
 164         .dram_sdcke1 = 0x3000,
 165         .dram_sdba2 = 0x00000000,
 166         .dram_sdodt0 = 0x30,
 167         .dram_sdodt1 = 0x30,
 168 };
 169
 170 /* configure MX6Q/DUAL mmdc GRP io registers */
 171 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 172         .grp_b0ds = 0x30,
 173         .grp_b1ds = 0x30,
 174         .grp_b2ds = 0x30,
 175         .grp_b3ds = 0x30,
 176         .grp_b4ds = 0x30,
 177         .grp_b5ds = 0x30,
 178         .grp_b6ds = 0x30,
 179         .grp_b7ds = 0x30,
 180         .grp_addds = 0x30,
 181         .grp_ddrmode_ctl = 0x00020000,
 182         .grp_ddrpke = 0x00000000,
 183         .grp_ddrmode = 0x00020000,
 184         .grp_ctlds = 0x30,
 185         .grp_ddr_type = 0x000c0000,
 186 };
 187
 188 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 189 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 190         .dram_sdclk_0 = 0x30,
 191         .dram_sdclk_1 = 0x30,
 192         .dram_cas = 0x30,
 193         .dram_ras = 0x30,
 194         .dram_reset = 0x30,
 195         .dram_sdcke0 = 0x30,
 196         .dram_sdcke1 = 0x30,
 197         .dram_sdba2 = 0x00000000,
 198         .dram_sdodt0 = 0x30,
 199         .dram_sdodt1 = 0x30,
 200         .dram_sdqs0 = 0x28,
 201         .dram_sdqs1 = 0x28,
 202         .dram_sdqs2 = 0x28,
 203         .dram_sdqs3 = 0x28,
 204         .dram_sdqs4 = 0x28,
 205         .dram_sdqs5 = 0x28,
 206         .dram_sdqs6 = 0x28,
 207         .dram_sdqs7 = 0x28,
 208         .dram_dqm0 = 0x28,
 209         .dram_dqm1 = 0x28,
 210         .dram_dqm2 = 0x28,
 211         .dram_dqm3 = 0x28,
 212         .dram_dqm4 = 0x28,
 213         .dram_dqm5 = 0x28,
 214         .dram_dqm6 = 0x28,
 215         .dram_dqm7 = 0x28,
 216 };
 217
 218 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 219 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 220         .grp_ddr_type = 0x000c0000,
 221         .grp_ddrmode_ctl = 0x00020000,
 222         .grp_ddrpke = 0x00000000,
 223         .grp_addds = 0x30,
 224         .grp_ctlds = 0x30,
 225         .grp_ddrmode = 0x00020000,
 226         .grp_b0ds = 0x28,
 227         .grp_b1ds = 0x28,
 228         .grp_b2ds = 0x28,
 229         .grp_b3ds = 0x28,
 230         .grp_b4ds = 0x28,
 231         .grp_b5ds = 0x28,
 232         .grp_b6ds = 0x28,
 233         .grp_b7ds = 0x28,
 234 };
 235
 236 /* mt41j256 */
 237 static struct mx6_ddr3_cfg mt41j256 = {
 238         .mem_speed = 1066,
 239         .density = 2,
 240         .width = 16,
 241         .banks = 8,
 242         .rowaddr = 13,
 243         .coladdr = 10,
 244         .pagesz = 2,
 245         .trcd = 1375,
 246         .trcmin = 4875,
 247         .trasmin = 3500,
 248         .SRT = 0,
 249 };
 250
 251 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
 252         .p0_mpwldectrl0 = 0x000E0009,
 253         .p0_mpwldectrl1 = 0x0018000E,
 254         .p1_mpwldectrl0 = 0x00000007,
 255         .p1_mpwldectrl1 = 0x00000000,
 256         .p0_mpdgctrl0 = 0x43280334,
 257         .p0_mpdgctrl1 = 0x031C0314,
 258         .p1_mpdgctrl0 = 0x4318031C,
 259         .p1_mpdgctrl1 = 0x030C0258,
 260         .p0_mprddlctl = 0x3E343A40,
 261         .p1_mprddlctl = 0x383C3844,
 262         .p0_mpwrdlctl = 0x40404440,
 263         .p1_mpwrdlctl = 0x4C3E4446,
 264 };
 265
 266 /* DDR 64bit */
 267 static struct mx6_ddr_sysinfo mem_q = {
 268         .ddr_type       = DDR_TYPE_DDR3,
 269         .dsize          = 2,
 270         .cs1_mirror     = 0,
 271         /* config for full 4GB range so that get_mem_size() works */
 272         .cs_density     = 32,
 273         .ncs            = 1,
 274         .bi_on          = 1,
 275         .rtt_nom        = 2,
 276         .rtt_wr         = 2,
 277         .ralat          = 5,
 278         .walat          = 0,
 279         .mif3_mode      = 3,
 280         .rst_to_cke     = 0x23,
 281         .sde_to_rst     = 0x10,
 282 };
 283
 284 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
 285         .p0_mpwldectrl0 = 0x001F0024,
 286         .p0_mpwldectrl1 = 0x00110018,
 287         .p1_mpwldectrl0 = 0x001F0024,
 288         .p1_mpwldectrl1 = 0x00110018,
 289         .p0_mpdgctrl0 = 0x4230022C,
 290         .p0_mpdgctrl1 = 0x02180220,
 291         .p1_mpdgctrl0 = 0x42440248,
 292         .p1_mpdgctrl1 = 0x02300238,
 293         .p0_mprddlctl = 0x44444A48,
 294         .p1_mprddlctl = 0x46484A42,
 295         .p0_mpwrdlctl = 0x38383234,
 296         .p1_mpwrdlctl = 0x3C34362E,
 297 };
 298
 299 /* DDR 64bit 1GB */
 300 static struct mx6_ddr_sysinfo mem_dl = {
 301         .dsize          = 2,
 302         .cs1_mirror     = 0,
 303         /* config for full 4GB range so that get_mem_size() works */
 304         .cs_density     = 32,
 305         .ncs            = 1,
 306         .bi_on          = 1,
 307         .rtt_nom        = 1,
 308         .rtt_wr         = 1,
 309         .ralat          = 5,
 310         .walat          = 0,
 311         .mif3_mode      = 3,
 312         .rst_to_cke     = 0x23,
 313         .sde_to_rst     = 0x10,
 314 };
 315
 316 /* DDR 32bit 512MB */
 317 static struct mx6_ddr_sysinfo mem_s = {
 318         .dsize          = 1,
 319         .cs1_mirror     = 0,
 320         /* config for full 4GB range so that get_mem_size() works */
 321         .cs_density     = 32,
 322         .ncs            = 1,
 323         .bi_on          = 1,
 324         .rtt_nom        = 1,
 325         .rtt_wr         = 1,
 326         .ralat          = 5,
 327         .walat          = 0,
 328         .mif3_mode      = 3,
 329         .rst_to_cke     = 0x23,
 330         .sde_to_rst     = 0x10,
 331 };
 332
 333 static void ccgr_init(void)
 334 {
 335         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 336
 337         writel(0x00003F3F, &ccm->CCGR0);
 338         writel(0x0030FC00, &ccm->CCGR1);
 339         writel(0x000FC000, &ccm->CCGR2);
 340         writel(0x3F300000, &ccm->CCGR3);
 341         writel(0xFF00F300, &ccm->CCGR4);
 342         writel(0x0F0000C3, &ccm->CCGR5);
 343         writel(0x000003CC, &ccm->CCGR6);
 344 }
 345
 346 static void gpr_init(void)
 347 {
 348         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 349
 350         /* enable AXI cache for VDOA/VPU/IPU */
 351         writel(0xF00000CF, &iomux->gpr[4]);
 352         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 353         writel(0x007F007F, &iomux->gpr[6]);
 354         writel(0x007F007F, &iomux->gpr[7]);
 355 }
 356
 357 static void spl_dram_init(void)
 358 {
 359         if (is_mx6solo()) {
 360                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 361                 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
 362         } else if (is_mx6dl()) {
 363                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 364                 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
 365         } else if (is_mx6dq()) {
 366                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 367                 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
 368         }
 369
 370         udelay(100);
 371 }
 372
 373 void board_init_f(ulong dummy)
 374 {
 375         ccgr_init();
 376
 377         /* setup AIPS and disable watchdog */
 378         arch_cpu_init();
 379
 380         gpr_init();
 381
 382         /* iomux */
 383         board_early_init_f();
 384
 385         /* setup GP timer */
 386         timer_init();
 387
 388         /* UART clocks enabled and gd valid - init serial console */
 389         preloader_console_init();
 390
 391         /* DDR initialization */
 392         spl_dram_init();
 393
 394         /* Clear the BSS. */
 395         memset(__bss_start, 0, __bss_end - __bss_start);
 396
 397         /* load/boot image from boot device */
 398         board_init_r(NULL, 0);
 399 }
 400 #endif