board/engicam/icorem6/icorem6.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <fsl_esdhc.h>
  11 #include <mmc.h>
  12 #include <miiphy.h>
  13 #include <netdev.h>
  14
  15 #include <asm/io.h>
  16 #include <asm/gpio.h>
  17 #include <linux/sizes.h>
  18
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/crm_regs.h>
  21 #include <asm/arch/iomux.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/imx-common/iomux-v3.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  29         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  30         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  31
  32 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  33         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  34         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  35
  36 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  37         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  38         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  39
  40 static iomux_v3_cfg_t const uart4_pads[] = {
  41         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  42         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  43 };
  44
  45 static iomux_v3_cfg_t const enet_pads[] = {
  46         IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  47         IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL | PAD_CTL_SRE_FAST)),
  48         IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  49         IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  50         IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  51         IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  52         IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  53         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  54         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  55         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  56 };
  57
  58 static iomux_v3_cfg_t const usdhc1_pads[] = {
  59         IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  60         IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  61         IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  62         IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  63         IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  64         IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  65         IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
  66 };
  67
  68 #ifdef CONFIG_FSL_ESDHC
  69 #define USDHC1_CD_GPIO  IMX_GPIO_NR(1, 1)
  70
  71 struct fsl_esdhc_cfg usdhc_cfg[1] = {
  72         {USDHC1_BASE_ADDR, 0, 4},
  73 };
  74
  75 int board_mmc_getcd(struct mmc *mmc)
  76 {
  77         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  78         int ret = 0;
  79
  80         switch (cfg->esdhc_base) {
  81         case USDHC1_BASE_ADDR:
  82                 ret = !gpio_get_value(USDHC1_CD_GPIO);
  83                 break;
  84         }
  85
  86         return ret;
  87 }
  88
  89 int board_mmc_init(bd_t *bis)
  90 {
  91         int i, ret;
  92
  93         /*
  94         * According to the board_mmc_init() the following map is done:
  95         * (U-boot device node)    (Physical Port)
  96         * mmc0                          USDHC1
  97         */
  98         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  99                 switch (i) {
 100                 case 0:
 101                         SETUP_IOMUX_PADS(usdhc1_pads);
 102                         gpio_direction_input(USDHC1_CD_GPIO);
 103                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 104                         break;
 105                 default:
 106                         printf("Warning - USDHC%d controller not supporting\n",
 107                                i + 1);
 108                         return 0;
 109                 }
 110
 111                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 112                 if (ret) {
 113                         printf("Warning: failed to initialize mmc dev %d\n", i);
 114                         return ret;
 115                 }
 116         }
 117
 118         return 0;
 119 }
 120 #endif
 121
 122 #ifdef CONFIG_FEC_MXC
 123 #define ENET_PHY_RST            IMX_GPIO_NR(7, 12)
 124 static int setup_fec(void)
 125 {
 126         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 127         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 128         s32 timeout = 100000;
 129         u32 reg = 0;
 130         int ret;
 131
 132         /* Enable fec clock */
 133         setbits_le32(&ccm->CCGR1, MXC_CCM_CCGR1_ENET_MASK);
 134
 135         /* use 50MHz */
 136         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 137         if (ret)
 138                 return ret;
 139
 140         /* Enable PLLs */
 141         reg = readl(&anatop->pll_enet);
 142         reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
 143         writel(reg, &anatop->pll_enet);
 144         reg = readl(&anatop->pll_enet);
 145         reg |= BM_ANADIG_PLL_SYS_ENABLE;
 146         while (timeout--) {
 147                 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
 148                         break;
 149         }
 150         if (timeout <= 0)
 151                 return -EIO;
 152         reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
 153         writel(reg, &anatop->pll_enet);
 154
 155         /* reset the phy */
 156         gpio_direction_output(ENET_PHY_RST, 0);
 157         udelay(10000);
 158         gpio_set_value(ENET_PHY_RST, 1);
 159
 160         return 0;
 161 }
 162
 163 int board_eth_init(bd_t *bis)
 164 {
 165         int ret;
 166
 167         SETUP_IOMUX_PADS(enet_pads);
 168         setup_fec();
 169
 170         return ret = cpu_eth_init(bis);
 171 }
 172 #endif
 173
 174 int board_early_init_f(void)
 175 {
 176         SETUP_IOMUX_PADS(uart4_pads);
 177
 178         return 0;
 179 }
 180
 181 int board_init(void)
 182 {
 183         /* Address of boot parameters */
 184         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 185
 186         return 0;
 187 }
 188
 189 int dram_init(void)
 190 {
 191         gd->ram_size = imx_ddr_size();
 192
 193         return 0;
 194 }
 195
 196 #ifdef CONFIG_SPL_BUILD
 197 #include <libfdt.h>
 198 #include <spl.h>
 199
 200 #include <asm/arch/crm_regs.h>
 201 #include <asm/arch/mx6-ddr.h>
 202
 203 /*
 204  * Driving strength:
 205  *   0x30 == 40 Ohm
 206  *   0x28 == 48 Ohm
 207  */
 208
 209 #define IMX6DQ_DRIVE_STRENGTH           0x30
 210 #define IMX6SDL_DRIVE_STRENGTH          0x28
 211
 212 /* configure MX6Q/DUAL mmdc DDR io registers */
 213 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 214         .dram_sdqs0 = 0x28,
 215         .dram_sdqs1 = 0x28,
 216         .dram_sdqs2 = 0x28,
 217         .dram_sdqs3 = 0x28,
 218         .dram_sdqs4 = 0x28,
 219         .dram_sdqs5 = 0x28,
 220         .dram_sdqs6 = 0x28,
 221         .dram_sdqs7 = 0x28,
 222         .dram_dqm0 = 0x28,
 223         .dram_dqm1 = 0x28,
 224         .dram_dqm2 = 0x28,
 225         .dram_dqm3 = 0x28,
 226         .dram_dqm4 = 0x28,
 227         .dram_dqm5 = 0x28,
 228         .dram_dqm6 = 0x28,
 229         .dram_dqm7 = 0x28,
 230         .dram_cas = 0x30,
 231         .dram_ras = 0x30,
 232         .dram_sdclk_0 = 0x30,
 233         .dram_sdclk_1 = 0x30,
 234         .dram_reset = 0x30,
 235         .dram_sdcke0 = 0x3000,
 236         .dram_sdcke1 = 0x3000,
 237         .dram_sdba2 = 0x00000000,
 238         .dram_sdodt0 = 0x30,
 239         .dram_sdodt1 = 0x30,
 240 };
 241
 242 /* configure MX6Q/DUAL mmdc GRP io registers */
 243 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 244         .grp_b0ds = 0x30,
 245         .grp_b1ds = 0x30,
 246         .grp_b2ds = 0x30,
 247         .grp_b3ds = 0x30,
 248         .grp_b4ds = 0x30,
 249         .grp_b5ds = 0x30,
 250         .grp_b6ds = 0x30,
 251         .grp_b7ds = 0x30,
 252         .grp_addds = 0x30,
 253         .grp_ddrmode_ctl = 0x00020000,
 254         .grp_ddrpke = 0x00000000,
 255         .grp_ddrmode = 0x00020000,
 256         .grp_ctlds = 0x30,
 257         .grp_ddr_type = 0x000c0000,
 258 };
 259
 260 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 261 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 262         .dram_sdclk_0 = 0x30,
 263         .dram_sdclk_1 = 0x30,
 264         .dram_cas = 0x30,
 265         .dram_ras = 0x30,
 266         .dram_reset = 0x30,
 267         .dram_sdcke0 = 0x30,
 268         .dram_sdcke1 = 0x30,
 269         .dram_sdba2 = 0x00000000,
 270         .dram_sdodt0 = 0x30,
 271         .dram_sdodt1 = 0x30,
 272         .dram_sdqs0 = 0x28,
 273         .dram_sdqs1 = 0x28,
 274         .dram_sdqs2 = 0x28,
 275         .dram_sdqs3 = 0x28,
 276         .dram_sdqs4 = 0x28,
 277         .dram_sdqs5 = 0x28,
 278         .dram_sdqs6 = 0x28,
 279         .dram_sdqs7 = 0x28,
 280         .dram_dqm0 = 0x28,
 281         .dram_dqm1 = 0x28,
 282         .dram_dqm2 = 0x28,
 283         .dram_dqm3 = 0x28,
 284         .dram_dqm4 = 0x28,
 285         .dram_dqm5 = 0x28,
 286         .dram_dqm6 = 0x28,
 287         .dram_dqm7 = 0x28,
 288 };
 289
 290 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 291 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 292         .grp_ddr_type = 0x000c0000,
 293         .grp_ddrmode_ctl = 0x00020000,
 294         .grp_ddrpke = 0x00000000,
 295         .grp_addds = 0x30,
 296         .grp_ctlds = 0x30,
 297         .grp_ddrmode = 0x00020000,
 298         .grp_b0ds = 0x28,
 299         .grp_b1ds = 0x28,
 300         .grp_b2ds = 0x28,
 301         .grp_b3ds = 0x28,
 302         .grp_b4ds = 0x28,
 303         .grp_b5ds = 0x28,
 304         .grp_b6ds = 0x28,
 305         .grp_b7ds = 0x28,
 306 };
 307
 308 /* mt41j256 */
 309 static struct mx6_ddr3_cfg mt41j256 = {
 310         .mem_speed = 1066,
 311         .density = 2,
 312         .width = 16,
 313         .banks = 8,
 314         .rowaddr = 13,
 315         .coladdr = 10,
 316         .pagesz = 2,
 317         .trcd = 1375,
 318         .trcmin = 4875,
 319         .trasmin = 3500,
 320         .SRT = 0,
 321 };
 322
 323 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
 324         .p0_mpwldectrl0 = 0x000E0009,
 325         .p0_mpwldectrl1 = 0x0018000E,
 326         .p1_mpwldectrl0 = 0x00000007,
 327         .p1_mpwldectrl1 = 0x00000000,
 328         .p0_mpdgctrl0 = 0x43280334,
 329         .p0_mpdgctrl1 = 0x031C0314,
 330         .p1_mpdgctrl0 = 0x4318031C,
 331         .p1_mpdgctrl1 = 0x030C0258,
 332         .p0_mprddlctl = 0x3E343A40,
 333         .p1_mprddlctl = 0x383C3844,
 334         .p0_mpwrdlctl = 0x40404440,
 335         .p1_mpwrdlctl = 0x4C3E4446,
 336 };
 337
 338 /* DDR 64bit */
 339 static struct mx6_ddr_sysinfo mem_q = {
 340         .ddr_type       = DDR_TYPE_DDR3,
 341         .dsize          = 2,
 342         .cs1_mirror     = 0,
 343         /* config for full 4GB range so that get_mem_size() works */
 344         .cs_density     = 32,
 345         .ncs            = 1,
 346         .bi_on          = 1,
 347         .rtt_nom        = 2,
 348         .rtt_wr         = 2,
 349         .ralat          = 5,
 350         .walat          = 0,
 351         .mif3_mode      = 3,
 352         .rst_to_cke     = 0x23,
 353         .sde_to_rst     = 0x10,
 354 };
 355
 356 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
 357         .p0_mpwldectrl0 = 0x001F0024,
 358         .p0_mpwldectrl1 = 0x00110018,
 359         .p1_mpwldectrl0 = 0x001F0024,
 360         .p1_mpwldectrl1 = 0x00110018,
 361         .p0_mpdgctrl0 = 0x4230022C,
 362         .p0_mpdgctrl1 = 0x02180220,
 363         .p1_mpdgctrl0 = 0x42440248,
 364         .p1_mpdgctrl1 = 0x02300238,
 365         .p0_mprddlctl = 0x44444A48,
 366         .p1_mprddlctl = 0x46484A42,
 367         .p0_mpwrdlctl = 0x38383234,
 368         .p1_mpwrdlctl = 0x3C34362E,
 369 };
 370
 371 /* DDR 64bit 1GB */
 372 static struct mx6_ddr_sysinfo mem_dl = {
 373         .dsize          = 2,
 374         .cs1_mirror     = 0,
 375         /* config for full 4GB range so that get_mem_size() works */
 376         .cs_density     = 32,
 377         .ncs            = 1,
 378         .bi_on          = 1,
 379         .rtt_nom        = 1,
 380         .rtt_wr         = 1,
 381         .ralat          = 5,
 382         .walat          = 0,
 383         .mif3_mode      = 3,
 384         .rst_to_cke     = 0x23,
 385         .sde_to_rst     = 0x10,
 386 };
 387
 388 /* DDR 32bit 512MB */
 389 static struct mx6_ddr_sysinfo mem_s = {
 390         .dsize          = 1,
 391         .cs1_mirror     = 0,
 392         /* config for full 4GB range so that get_mem_size() works */
 393         .cs_density     = 32,
 394         .ncs            = 1,
 395         .bi_on          = 1,
 396         .rtt_nom        = 1,
 397         .rtt_wr         = 1,
 398         .ralat          = 5,
 399         .walat          = 0,
 400         .mif3_mode      = 3,
 401         .rst_to_cke     = 0x23,
 402         .sde_to_rst     = 0x10,
 403 };
 404
 405 static void ccgr_init(void)
 406 {
 407         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 408
 409         writel(0x00003F3F, &ccm->CCGR0);
 410         writel(0x0030FC00, &ccm->CCGR1);
 411         writel(0x000FC000, &ccm->CCGR2);
 412         writel(0x3F300000, &ccm->CCGR3);
 413         writel(0xFF00F300, &ccm->CCGR4);
 414         writel(0x0F0000C3, &ccm->CCGR5);
 415         writel(0x000003CC, &ccm->CCGR6);
 416 }
 417
 418 static void gpr_init(void)
 419 {
 420         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 421
 422         /* enable AXI cache for VDOA/VPU/IPU */
 423         writel(0xF00000CF, &iomux->gpr[4]);
 424         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 425         writel(0x007F007F, &iomux->gpr[6]);
 426         writel(0x007F007F, &iomux->gpr[7]);
 427 }
 428
 429 static void spl_dram_init(void)
 430 {
 431         if (is_mx6solo()) {
 432                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 433                 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
 434         } else if (is_mx6dl()) {
 435                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 436                 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
 437         } else if (is_mx6dq()) {
 438                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 439                 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
 440         }
 441
 442         udelay(100);
 443 }
 444
 445 void board_init_f(ulong dummy)
 446 {
 447         ccgr_init();
 448
 449         /* setup AIPS and disable watchdog */
 450         arch_cpu_init();
 451
 452         gpr_init();
 453
 454         /* iomux */
 455         board_early_init_f();
 456
 457         /* setup GP timer */
 458         timer_init();
 459
 460         /* UART clocks enabled and gd valid - init serial console */
 461         preloader_console_init();
 462
 463         /* DDR initialization */
 464         spl_dram_init();
 465
 466         /* Clear the BSS. */
 467         memset(__bss_start, 0, __bss_end - __bss_start);
 468
 469         /* load/boot image from boot device */
 470         board_init_r(NULL, 0);
 471 }
 472 #endif