board/engicam/icorem6/icorem6.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <miiphy.h>
  11 #include <netdev.h>
  12
  13 #include <asm/io.h>
  14 #include <asm/gpio.h>
  15 #include <linux/sizes.h>
  16
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/crm_regs.h>
  19 #include <asm/arch/iomux.h>
  20 #include <asm/arch/mx6-pins.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/imx-common/iomux-v3.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  27         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  28         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  29
  30 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  31         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  32         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  33
  34 static iomux_v3_cfg_t const uart4_pads[] = {
  35         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  36         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  37 };
  38
  39 static iomux_v3_cfg_t const enet_pads[] = {
  40         IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  41         IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL | PAD_CTL_SRE_FAST)),
  42         IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  43         IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  44         IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  45         IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  46         IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  47         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  48         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  49         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  50 };
  51
  52 #ifdef CONFIG_FEC_MXC
  53 #define ENET_PHY_RST            IMX_GPIO_NR(7, 12)
  54 static int setup_fec(void)
  55 {
  56         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  57         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  58         s32 timeout = 100000;
  59         u32 reg = 0;
  60         int ret;
  61
  62         /* Enable fec clock */
  63         setbits_le32(&ccm->CCGR1, MXC_CCM_CCGR1_ENET_MASK);
  64
  65         /* use 50MHz */
  66         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
  67         if (ret)
  68                 return ret;
  69
  70         /* Enable PLLs */
  71         reg = readl(&anatop->pll_enet);
  72         reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
  73         writel(reg, &anatop->pll_enet);
  74         reg = readl(&anatop->pll_enet);
  75         reg |= BM_ANADIG_PLL_SYS_ENABLE;
  76         while (timeout--) {
  77                 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
  78                         break;
  79         }
  80         if (timeout <= 0)
  81                 return -EIO;
  82         reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
  83         writel(reg, &anatop->pll_enet);
  84
  85         /* reset the phy */
  86         gpio_direction_output(ENET_PHY_RST, 0);
  87         udelay(10000);
  88         gpio_set_value(ENET_PHY_RST, 1);
  89
  90         return 0;
  91 }
  92
  93 int board_eth_init(bd_t *bis)
  94 {
  95         int ret;
  96
  97         SETUP_IOMUX_PADS(enet_pads);
  98         setup_fec();
  99
 100         return ret = cpu_eth_init(bis);
 101 }
 102 #endif
 103
 104 int board_early_init_f(void)
 105 {
 106         SETUP_IOMUX_PADS(uart4_pads);
 107
 108         return 0;
 109 }
 110
 111 int board_init(void)
 112 {
 113         /* Address of boot parameters */
 114         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 115
 116         return 0;
 117 }
 118
 119 int dram_init(void)
 120 {
 121         gd->ram_size = imx_ddr_size();
 122
 123         return 0;
 124 }
 125
 126 #ifdef CONFIG_SPL_BUILD
 127 #include <libfdt.h>
 128 #include <spl.h>
 129
 130 #include <asm/arch/crm_regs.h>
 131 #include <asm/arch/mx6-ddr.h>
 132
 133 /* MMC board initialization is needed till adding DM support in SPL */
 134 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
 135 #include <mmc.h>
 136 #include <fsl_esdhc.h>
 137
 138 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 139         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
 140         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 141
 142 static iomux_v3_cfg_t const usdhc1_pads[] = {
 143         IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 144         IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 145         IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 146         IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 147         IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 148         IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 149         IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
 150 };
 151
 152 #define USDHC1_CD_GPIO  IMX_GPIO_NR(1, 1)
 153
 154 struct fsl_esdhc_cfg usdhc_cfg[1] = {
 155         {USDHC1_BASE_ADDR, 0, 4},
 156 };
 157
 158 int board_mmc_getcd(struct mmc *mmc)
 159 {
 160         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 161         int ret = 0;
 162
 163         switch (cfg->esdhc_base) {
 164         case USDHC1_BASE_ADDR:
 165                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 166                 break;
 167         }
 168
 169         return ret;
 170 }
 171
 172 int board_mmc_init(bd_t *bis)
 173 {
 174         int i, ret;
 175
 176         /*
 177         * According to the board_mmc_init() the following map is done:
 178         * (U-boot device node)    (Physical Port)
 179         * mmc0                          USDHC1
 180         */
 181         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 182                 switch (i) {
 183                 case 0:
 184                         SETUP_IOMUX_PADS(usdhc1_pads);
 185                         gpio_direction_input(USDHC1_CD_GPIO);
 186                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 187                         break;
 188                 default:
 189                         printf("Warning - USDHC%d controller not supporting\n",
 190                                i + 1);
 191                         return 0;
 192                 }
 193
 194                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 195                 if (ret) {
 196                         printf("Warning: failed to initialize mmc dev %d\n", i);
 197                         return ret;
 198                 }
 199         }
 200
 201         return 0;
 202 }
 203 #endif
 204
 205 /*
 206  * Driving strength:
 207  *   0x30 == 40 Ohm
 208  *   0x28 == 48 Ohm
 209  */
 210
 211 #define IMX6DQ_DRIVE_STRENGTH           0x30
 212 #define IMX6SDL_DRIVE_STRENGTH          0x28
 213
 214 /* configure MX6Q/DUAL mmdc DDR io registers */
 215 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 216         .dram_sdqs0 = 0x28,
 217         .dram_sdqs1 = 0x28,
 218         .dram_sdqs2 = 0x28,
 219         .dram_sdqs3 = 0x28,
 220         .dram_sdqs4 = 0x28,
 221         .dram_sdqs5 = 0x28,
 222         .dram_sdqs6 = 0x28,
 223         .dram_sdqs7 = 0x28,
 224         .dram_dqm0 = 0x28,
 225         .dram_dqm1 = 0x28,
 226         .dram_dqm2 = 0x28,
 227         .dram_dqm3 = 0x28,
 228         .dram_dqm4 = 0x28,
 229         .dram_dqm5 = 0x28,
 230         .dram_dqm6 = 0x28,
 231         .dram_dqm7 = 0x28,
 232         .dram_cas = 0x30,
 233         .dram_ras = 0x30,
 234         .dram_sdclk_0 = 0x30,
 235         .dram_sdclk_1 = 0x30,
 236         .dram_reset = 0x30,
 237         .dram_sdcke0 = 0x3000,
 238         .dram_sdcke1 = 0x3000,
 239         .dram_sdba2 = 0x00000000,
 240         .dram_sdodt0 = 0x30,
 241         .dram_sdodt1 = 0x30,
 242 };
 243
 244 /* configure MX6Q/DUAL mmdc GRP io registers */
 245 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 246         .grp_b0ds = 0x30,
 247         .grp_b1ds = 0x30,
 248         .grp_b2ds = 0x30,
 249         .grp_b3ds = 0x30,
 250         .grp_b4ds = 0x30,
 251         .grp_b5ds = 0x30,
 252         .grp_b6ds = 0x30,
 253         .grp_b7ds = 0x30,
 254         .grp_addds = 0x30,
 255         .grp_ddrmode_ctl = 0x00020000,
 256         .grp_ddrpke = 0x00000000,
 257         .grp_ddrmode = 0x00020000,
 258         .grp_ctlds = 0x30,
 259         .grp_ddr_type = 0x000c0000,
 260 };
 261
 262 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 263 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 264         .dram_sdclk_0 = 0x30,
 265         .dram_sdclk_1 = 0x30,
 266         .dram_cas = 0x30,
 267         .dram_ras = 0x30,
 268         .dram_reset = 0x30,
 269         .dram_sdcke0 = 0x30,
 270         .dram_sdcke1 = 0x30,
 271         .dram_sdba2 = 0x00000000,
 272         .dram_sdodt0 = 0x30,
 273         .dram_sdodt1 = 0x30,
 274         .dram_sdqs0 = 0x28,
 275         .dram_sdqs1 = 0x28,
 276         .dram_sdqs2 = 0x28,
 277         .dram_sdqs3 = 0x28,
 278         .dram_sdqs4 = 0x28,
 279         .dram_sdqs5 = 0x28,
 280         .dram_sdqs6 = 0x28,
 281         .dram_sdqs7 = 0x28,
 282         .dram_dqm0 = 0x28,
 283         .dram_dqm1 = 0x28,
 284         .dram_dqm2 = 0x28,
 285         .dram_dqm3 = 0x28,
 286         .dram_dqm4 = 0x28,
 287         .dram_dqm5 = 0x28,
 288         .dram_dqm6 = 0x28,
 289         .dram_dqm7 = 0x28,
 290 };
 291
 292 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 293 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 294         .grp_ddr_type = 0x000c0000,
 295         .grp_ddrmode_ctl = 0x00020000,
 296         .grp_ddrpke = 0x00000000,
 297         .grp_addds = 0x30,
 298         .grp_ctlds = 0x30,
 299         .grp_ddrmode = 0x00020000,
 300         .grp_b0ds = 0x28,
 301         .grp_b1ds = 0x28,
 302         .grp_b2ds = 0x28,
 303         .grp_b3ds = 0x28,
 304         .grp_b4ds = 0x28,
 305         .grp_b5ds = 0x28,
 306         .grp_b6ds = 0x28,
 307         .grp_b7ds = 0x28,
 308 };
 309
 310 /* mt41j256 */
 311 static struct mx6_ddr3_cfg mt41j256 = {
 312         .mem_speed = 1066,
 313         .density = 2,
 314         .width = 16,
 315         .banks = 8,
 316         .rowaddr = 13,
 317         .coladdr = 10,
 318         .pagesz = 2,
 319         .trcd = 1375,
 320         .trcmin = 4875,
 321         .trasmin = 3500,
 322         .SRT = 0,
 323 };
 324
 325 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
 326         .p0_mpwldectrl0 = 0x000E0009,
 327         .p0_mpwldectrl1 = 0x0018000E,
 328         .p1_mpwldectrl0 = 0x00000007,
 329         .p1_mpwldectrl1 = 0x00000000,
 330         .p0_mpdgctrl0 = 0x43280334,
 331         .p0_mpdgctrl1 = 0x031C0314,
 332         .p1_mpdgctrl0 = 0x4318031C,
 333         .p1_mpdgctrl1 = 0x030C0258,
 334         .p0_mprddlctl = 0x3E343A40,
 335         .p1_mprddlctl = 0x383C3844,
 336         .p0_mpwrdlctl = 0x40404440,
 337         .p1_mpwrdlctl = 0x4C3E4446,
 338 };
 339
 340 /* DDR 64bit */
 341 static struct mx6_ddr_sysinfo mem_q = {
 342         .ddr_type       = DDR_TYPE_DDR3,
 343         .dsize          = 2,
 344         .cs1_mirror     = 0,
 345         /* config for full 4GB range so that get_mem_size() works */
 346         .cs_density     = 32,
 347         .ncs            = 1,
 348         .bi_on          = 1,
 349         .rtt_nom        = 2,
 350         .rtt_wr         = 2,
 351         .ralat          = 5,
 352         .walat          = 0,
 353         .mif3_mode      = 3,
 354         .rst_to_cke     = 0x23,
 355         .sde_to_rst     = 0x10,
 356 };
 357
 358 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
 359         .p0_mpwldectrl0 = 0x001F0024,
 360         .p0_mpwldectrl1 = 0x00110018,
 361         .p1_mpwldectrl0 = 0x001F0024,
 362         .p1_mpwldectrl1 = 0x00110018,
 363         .p0_mpdgctrl0 = 0x4230022C,
 364         .p0_mpdgctrl1 = 0x02180220,
 365         .p1_mpdgctrl0 = 0x42440248,
 366         .p1_mpdgctrl1 = 0x02300238,
 367         .p0_mprddlctl = 0x44444A48,
 368         .p1_mprddlctl = 0x46484A42,
 369         .p0_mpwrdlctl = 0x38383234,
 370         .p1_mpwrdlctl = 0x3C34362E,
 371 };
 372
 373 /* DDR 64bit 1GB */
 374 static struct mx6_ddr_sysinfo mem_dl = {
 375         .dsize          = 2,
 376         .cs1_mirror     = 0,
 377         /* config for full 4GB range so that get_mem_size() works */
 378         .cs_density     = 32,
 379         .ncs            = 1,
 380         .bi_on          = 1,
 381         .rtt_nom        = 1,
 382         .rtt_wr         = 1,
 383         .ralat          = 5,
 384         .walat          = 0,
 385         .mif3_mode      = 3,
 386         .rst_to_cke     = 0x23,
 387         .sde_to_rst     = 0x10,
 388 };
 389
 390 /* DDR 32bit 512MB */
 391 static struct mx6_ddr_sysinfo mem_s = {
 392         .dsize          = 1,
 393         .cs1_mirror     = 0,
 394         /* config for full 4GB range so that get_mem_size() works */
 395         .cs_density     = 32,
 396         .ncs            = 1,
 397         .bi_on          = 1,
 398         .rtt_nom        = 1,
 399         .rtt_wr         = 1,
 400         .ralat          = 5,
 401         .walat          = 0,
 402         .mif3_mode      = 3,
 403         .rst_to_cke     = 0x23,
 404         .sde_to_rst     = 0x10,
 405 };
 406
 407 static void ccgr_init(void)
 408 {
 409         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 410
 411         writel(0x00003F3F, &ccm->CCGR0);
 412         writel(0x0030FC00, &ccm->CCGR1);
 413         writel(0x000FC000, &ccm->CCGR2);
 414         writel(0x3F300000, &ccm->CCGR3);
 415         writel(0xFF00F300, &ccm->CCGR4);
 416         writel(0x0F0000C3, &ccm->CCGR5);
 417         writel(0x000003CC, &ccm->CCGR6);
 418 }
 419
 420 static void gpr_init(void)
 421 {
 422         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 423
 424         /* enable AXI cache for VDOA/VPU/IPU */
 425         writel(0xF00000CF, &iomux->gpr[4]);
 426         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 427         writel(0x007F007F, &iomux->gpr[6]);
 428         writel(0x007F007F, &iomux->gpr[7]);
 429 }
 430
 431 static void spl_dram_init(void)
 432 {
 433         if (is_mx6solo()) {
 434                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 435                 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
 436         } else if (is_mx6dl()) {
 437                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 438                 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
 439         } else if (is_mx6dq()) {
 440                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 441                 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
 442         }
 443
 444         udelay(100);
 445 }
 446
 447 void board_init_f(ulong dummy)
 448 {
 449         ccgr_init();
 450
 451         /* setup AIPS and disable watchdog */
 452         arch_cpu_init();
 453
 454         gpr_init();
 455
 456         /* iomux */
 457         board_early_init_f();
 458
 459         /* setup GP timer */
 460         timer_init();
 461
 462         /* UART clocks enabled and gd valid - init serial console */
 463         preloader_console_init();
 464
 465         /* DDR initialization */
 466         spl_dram_init();
 467
 468         /* Clear the BSS. */
 469         memset(__bss_start, 0, __bss_end - __bss_start);
 470
 471         /* load/boot image from boot device */
 472         board_init_r(NULL, 0);
 473 }
 474 #endif