board/embest/mx6boards/mx6boards.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Eukréa Electromatique
   4  * Author: Eric Bénard <eric@eukrea.com>
   5  *         Fabio Estevam <fabio.estevam@freescale.com>
   6  *         Jon Nettleton <jon.nettleton@gmail.com>
   7  *
   8  * based on sabresd.c which is :
   9  * Copyright (C) 2012 Freescale Semiconductor, Inc.
  10  * and on hummingboard.c which is :
  11  * Copyright (C) 2013 SolidRun ltd.
  12  * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
  13  */
  14
  15 #include <common.h>
  16 #include <init.h>
  17 #include <net.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/arch/imx-regs.h>
  21 #include <asm/arch/iomux.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/global_data.h>
  24 #include <linux/delay.h>
  25 #include <linux/errno.h>
  26 #include <asm/gpio.h>
  27 #include <asm/mach-imx/iomux-v3.h>
  28 #include <asm/mach-imx/boot_mode.h>
  29 #include <asm/mach-imx/mxc_i2c.h>
  30 #include <asm/mach-imx/spi.h>
  31 #include <asm/mach-imx/video.h>
  32 #include <i2c.h>
  33 #include <input.h>
  34 #include <miiphy.h>
  35 #include <netdev.h>
  36 #include <asm/arch/mxc_hdmi.h>
  37 #include <asm/arch/crm_regs.h>
  38 #include <linux/fb.h>
  39 #include <ipu_pixfmt.h>
  40 #include <asm/io.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  46         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  49         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  50         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  51
  52 #define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW |         \
  53         PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST |                  \
  54         PAD_CTL_HYS)
  55
  56 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  58
  59 #define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |              \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  61
  62 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  63         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  64
  65 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  66         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  67         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  68
  69 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  70                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  71
  72 static int board_type = -1;
  73 #define BOARD_IS_MARSBOARD      0
  74 #define BOARD_IS_RIOTBOARD      1
  75
  76 int dram_init(void)
  77 {
  78         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  79
  80         return 0;
  81 }
  82
  83 static iomux_v3_cfg_t const uart2_pads[] = {
  84         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  85         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  86 };
  87
  88 static void setup_iomux_uart(void)
  89 {
  90         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  91 }
  92
  93 iomux_v3_cfg_t const enet_pads[] = {
  94         /* AR8035 PHY Reset */
  95         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  96         /* AR8035 PHY Interrupt */
  97         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  98 };
  99
 100 static void setup_iomux_enet(void)
 101 {
 102         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 103
 104         /* Reset AR8035 PHY */
 105         gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
 106         mdelay(2);
 107         gpio_set_value(IMX_GPIO_NR(3, 31), 1);
 108 }
 109
 110 int mx6_rgmii_rework(struct phy_device *phydev)
 111 {
 112         /* from linux/arch/arm/mach-imx/mach-imx6q.c :
 113          * Ar803x phy SmartEEE feature cause link status generates glitch,
 114          * which cause ethernet link down/up issue, so disable SmartEEE
 115          */
 116         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 117         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 118         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 119
 120         return 0;
 121 }
 122
 123 int board_phy_config(struct phy_device *phydev)
 124 {
 125         mx6_rgmii_rework(phydev);
 126
 127         if (phydev->drv->config)
 128                 phydev->drv->config(phydev);
 129
 130         return 0;
 131 }
 132
 133 #ifdef CONFIG_MXC_SPI
 134 iomux_v3_cfg_t const ecspi1_pads[] = {
 135         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 136         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 137         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 138         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 139 };
 140
 141 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 142 {
 143         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
 144 }
 145
 146 static void setup_spi(void)
 147 {
 148         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 149 }
 150 #endif
 151
 152 struct i2c_pads_info i2c_pad_info1 = {
 153         .scl = {
 154                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
 155                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 156                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
 157                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 158                 .gp = IMX_GPIO_NR(5, 27)
 159         },
 160         .sda = {
 161                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
 162                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 163                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
 164                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 165                 .gp = IMX_GPIO_NR(5, 26)
 166         }
 167 };
 168
 169 struct i2c_pads_info i2c_pad_info2 = {
 170         .scl = {
 171                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
 172                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 173                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
 174                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 175                 .gp = IMX_GPIO_NR(4, 12)
 176         },
 177         .sda = {
 178                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
 179                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 180                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
 181                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 182                 .gp = IMX_GPIO_NR(4, 13)
 183         }
 184 };
 185
 186 struct i2c_pads_info i2c_pad_info3 = {
 187         .scl = {
 188                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
 189                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 190                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
 191                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 192                 .gp = IMX_GPIO_NR(1, 5)
 193         },
 194         .sda = {
 195                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
 196                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 197                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
 198                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 199                 .gp = IMX_GPIO_NR(1, 6)
 200         }
 201 };
 202
 203 iomux_v3_cfg_t const tft_pads_riot[] = {
 204         /* LCD_PWR_EN */
 205         MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 206         /* TOUCH_INT */
 207         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 208         /* LED_PWR_EN */
 209         MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 210         /* BL LEVEL */
 211         MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 212 };
 213
 214 iomux_v3_cfg_t const tft_pads_mars[] = {
 215         /* LCD_PWR_EN */
 216         MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 217         /* TOUCH_INT */
 218         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 219         /* LED_PWR_EN */
 220         MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 221         /* BL LEVEL (PWM4) */
 222         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 223 };
 224
 225 #if defined(CONFIG_VIDEO_IPUV3)
 226
 227 static void enable_lvds(struct display_info_t const *dev)
 228 {
 229         struct iomuxc *iomux = (struct iomuxc *)
 230                                 IOMUXC_BASE_ADDR;
 231         setbits_le32(&iomux->gpr[2],
 232                      IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
 233         /* set backlight level to ON */
 234         if (board_type == BOARD_IS_RIOTBOARD)
 235                 gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
 236         else if (board_type == BOARD_IS_MARSBOARD)
 237                 gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
 238 }
 239
 240 static void disable_lvds(struct display_info_t const *dev)
 241 {
 242         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 243
 244         /* set backlight level to OFF */
 245         if (board_type == BOARD_IS_RIOTBOARD)
 246                 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
 247         else if (board_type == BOARD_IS_MARSBOARD)
 248                 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
 249
 250         clrbits_le32(&iomux->gpr[2],
 251                      IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
 252 }
 253
 254 static void do_enable_hdmi(struct display_info_t const *dev)
 255 {
 256         disable_lvds(dev);
 257         imx_enable_hdmi_phy();
 258 }
 259
 260 static int detect_i2c(struct display_info_t const *dev)
 261 {
 262         return (0 == i2c_set_bus_num(dev->bus)) &&
 263                 (0 == i2c_probe(dev->addr));
 264 }
 265
 266 struct display_info_t const displays[] = {{
 267         .bus    = -1,
 268         .addr   = 0,
 269         .pixfmt = IPU_PIX_FMT_RGB24,
 270         .detect = detect_hdmi,
 271         .enable = do_enable_hdmi,
 272         .mode   = {
 273                 .name           = "HDMI",
 274                 .refresh        = 60,
 275                 .xres           = 1024,
 276                 .yres           = 768,
 277                 .pixclock       = 15385,
 278                 .left_margin    = 220,
 279                 .right_margin   = 40,
 280                 .upper_margin   = 21,
 281                 .lower_margin   = 7,
 282                 .hsync_len      = 60,
 283                 .vsync_len      = 10,
 284                 .sync           = FB_SYNC_EXT,
 285                 .vmode          = FB_VMODE_NONINTERLACED
 286 } }, {
 287         .bus    = 2,
 288         .addr   = 0x1,
 289         .pixfmt = IPU_PIX_FMT_LVDS666,
 290         .detect = detect_i2c,
 291         .enable = enable_lvds,
 292         .mode   = {
 293                 .name           = "LCD8000-97C",
 294                 .refresh        = 60,
 295                 .xres           = 1024,
 296                 .yres           = 768,
 297                 .pixclock       = 15385,
 298                 .left_margin    = 100,
 299                 .right_margin   = 200,
 300                 .upper_margin   = 10,
 301                 .lower_margin   = 20,
 302                 .hsync_len      = 20,
 303                 .vsync_len      = 8,
 304                 .sync           = FB_SYNC_EXT,
 305                 .vmode          = FB_VMODE_NONINTERLACED
 306 } } };
 307 size_t display_count = ARRAY_SIZE(displays);
 308
 309 static void setup_display(void)
 310 {
 311         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 312         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 313         int reg;
 314
 315         enable_ipu_clock();
 316         imx_setup_hdmi();
 317
 318         /* Turn on LDB0, IPU,IPU DI0 clocks */
 319         setbits_le32(&mxc_ccm->CCGR3,
 320                      MXC_CCM_CCGR3_LDB_DI0_MASK);
 321
 322         /* set LDB0 clk select to 011/011 */
 323         clrsetbits_le32(&mxc_ccm->cs2cdr,
 324                         MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
 325                         (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
 326
 327         setbits_le32(&mxc_ccm->cscmr2,
 328                      MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 329
 330         setbits_le32(&mxc_ccm->chsccdr,
 331                      (CHSCCDR_CLK_SEL_LDB_DI0
 332                      << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 333
 334         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 335              | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 336              | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 337              | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 338              | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 339              | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 340              | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 341              | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 342         writel(reg, &iomux->gpr[2]);
 343
 344         clrsetbits_le32(&iomux->gpr[3],
 345                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 346                         IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
 347                         IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 348                         << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 349 }
 350 #endif /* CONFIG_VIDEO_IPUV3 */
 351
 352 /*
 353  * Do not overwrite the console
 354  * Use always serial for U-Boot console
 355  */
 356 int overwrite_console(void)
 357 {
 358         return 1;
 359 }
 360
 361 int board_early_init_f(void)
 362 {
 363         u32 cputype = cpu_type(get_cpu_rev());
 364
 365         switch (cputype) {
 366         case MXC_CPU_MX6SOLO:
 367                 board_type = BOARD_IS_RIOTBOARD;
 368                 break;
 369         case MXC_CPU_MX6D:
 370                 board_type = BOARD_IS_MARSBOARD;
 371                 break;
 372         }
 373
 374         setup_iomux_uart();
 375
 376         if (board_type == BOARD_IS_RIOTBOARD)
 377                 imx_iomux_v3_setup_multiple_pads(
 378                         tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
 379         else if (board_type == BOARD_IS_MARSBOARD)
 380                 imx_iomux_v3_setup_multiple_pads(
 381                         tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
 382 #if defined(CONFIG_VIDEO_IPUV3)
 383         /* power ON LCD */
 384         gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
 385         /* touch interrupt is an input */
 386         gpio_direction_input(IMX_GPIO_NR(6, 14));
 387         /* power ON backlight */
 388         gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
 389         /* set backlight level to off */
 390         if (board_type == BOARD_IS_RIOTBOARD)
 391                 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
 392         else if (board_type == BOARD_IS_MARSBOARD)
 393                 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
 394         setup_display();
 395 #endif
 396
 397         return 0;
 398 }
 399
 400 int board_init(void)
 401 {
 402         /* address of boot parameters */
 403         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 404         /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
 405         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 406         /* i2c2 : HDMI EDID */
 407         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 408         /* i2c3 : LVDS, Expansion connector */
 409         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 410 #ifdef CONFIG_MXC_SPI
 411         setup_spi();
 412 #endif
 413         return 0;
 414 }
 415
 416 #ifdef CONFIG_CMD_BMODE
 417 static const struct boot_mode riotboard_boot_modes[] = {
 418         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 419         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 420         {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 421         {NULL,   0},
 422 };
 423 static const struct boot_mode marsboard_boot_modes[] = {
 424         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 425         {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 426         {NULL,   0},
 427 };
 428 #endif
 429
 430 int board_late_init(void)
 431 {
 432 #ifdef CONFIG_CMD_BMODE
 433         if (board_type == BOARD_IS_RIOTBOARD)
 434                 add_board_boot_modes(riotboard_boot_modes);
 435         else if (board_type == BOARD_IS_RIOTBOARD)
 436                 add_board_boot_modes(marsboard_boot_modes);
 437 #endif
 438         setup_iomux_enet();
 439
 440         return 0;
 441 }
 442
 443 int checkboard(void)
 444 {
 445         puts("Board: ");
 446         if (board_type == BOARD_IS_MARSBOARD)
 447                 puts("MarSBoard\n");
 448         else if (board_type == BOARD_IS_RIOTBOARD)
 449                 puts("RIoTboard\n");
 450         else
 451                 printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
 452
 453         return 0;
 454 }
 455
 456 #ifdef CONFIG_SPL_BUILD
 457 #include <spl.h>
 458
 459 void board_init_f(ulong dummy)
 460 {
 461         u32 cputype = cpu_type(get_cpu_rev());
 462
 463         switch (cputype) {
 464         case MXC_CPU_MX6SOLO:
 465                 board_type = BOARD_IS_RIOTBOARD;
 466                 break;
 467         case MXC_CPU_MX6D:
 468                 board_type = BOARD_IS_MARSBOARD;
 469                 break;
 470         }
 471         arch_cpu_init();
 472
 473         /* setup GP timer */
 474         timer_init();
 475
 476 #ifdef CONFIG_SPL_SERIAL
 477         setup_iomux_uart();
 478         preloader_console_init();
 479 #endif
 480 }
 481
 482 void board_boot_order(u32 *spl_boot_list)
 483 {
 484         spl_boot_list[0] = BOOT_DEVICE_MMC1;
 485 }
 486
 487 /*
 488  * In order to jump to standard u-boot shell, you have to connect pin 5 of J13
 489  * to pin 3 (ground).
 490  */
 491 int spl_start_uboot(void)
 492 {
 493         int gpio_key = IMX_GPIO_NR(4, 16);
 494
 495         gpio_direction_input(gpio_key);
 496         if (gpio_get_value(gpio_key) == 0)
 497                 return 1;
 498         else
 499                 return 0;
 500 }
 501
 502 #endif