2 * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
4 * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include "sdram_cfg.h"
27 #include "early_udelay.h"
29 #define PROGRAM_MODE_REG(bank) (*(volatile uint32_t *) \
30 (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
32 #define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \
33 (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank))
35 static void force_precharge(void);
36 static void setup_refresh_timer(void);
37 static void program_mode_registers(void);
41 struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
43 writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG);
45 /* Issue continous NOP commands */
46 writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
52 setup_refresh_timer();
54 program_mode_registers();
56 /* Select normal operation mode */
57 writel(GLCONFIG_CKE, &sdram->glconfig);
60 static void force_precharge(void)
63 * Errata most EP93xx revisions say that PRECHARGE ALL isn't always
66 * Do a read from each bank to make sure they're precharged
75 static void setup_refresh_timer(void)
77 struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
79 /* Load refresh timer with 10 to issue refresh every 10 cycles */
80 writel(0x0a, &sdram->refrshtimr);
83 * Wait at least 80 clock cycles to provide 8 refresh cycles
89 * Program refresh timer with normal value
90 * We need 8192 refresh cycles every 64ms
91 * at 15ns (HCLK >= 66MHz) per cycle:
92 * 64ms / 8192 = 7.8125us
93 * 7.8125us / 15ns = 520 (0x208)
96 * TODO: redboot uses 0x1e0 for the slowest possible device
97 * but i don't understand how this value is calculated
99 writel(0x208, &sdram->refrshtimr);
102 static void program_mode_registers(void)
105 * The mode registers are programmed by performing a read from each
106 * SDRAM bank. The value of the address that is read defines the value
107 * that is written into the mode register
112 #if (CONFIG_NR_DRAM_BANKS >= 2)
116 #if (CONFIG_NR_DRAM_BANKS >= 3)
120 #if (CONFIG_NR_DRAM_BANKS == 4)