board/dhelectronics/dh_stm32mp1/board.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <adc.h>
   8 #include <log.h>
   9 #include <net.h>
  10 #include <asm/arch/stm32.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/gpio.h>
  13 #include <asm/io.h>
  14 #include <bootm.h>
  15 #include <clk.h>
  16 #include <config.h>
  17 #include <dm.h>
  18 #include <dm/device.h>
  19 #include <dm/uclass.h>
  20 #include <env.h>
  21 #include <env_internal.h>
  22 #include <g_dnl.h>
  23 #include <generic-phy.h>
  24 #include <hang.h>
  25 #include <i2c.h>
  26 #include <i2c_eeprom.h>
  27 #include <init.h>
  28 #include <led.h>
  29 #include <memalign.h>
  30 #include <misc.h>
  31 #include <mtd.h>
  32 #include <mtd_node.h>
  33 #include <netdev.h>
  34 #include <phy.h>
  35 #include <linux/bitops.h>
  36 #include <linux/delay.h>
  37 #include <power/regulator.h>
  38 #include <remoteproc.h>
  39 #include <reset.h>
  40 #include <syscon.h>
  41 #include <usb.h>
  42 #include <usb/dwc2_udc.h>
  43 #include <watchdog.h>
  44 #include "../../st/common/stpmic1.h"
  45
  46 /* SYSCFG registers */
  47 #define SYSCFG_BOOTR            0x00
  48 #define SYSCFG_PMCSETR          0x04
  49 #define SYSCFG_IOCTRLSETR       0x18
  50 #define SYSCFG_ICNR             0x1C
  51 #define SYSCFG_CMPCR            0x20
  52 #define SYSCFG_CMPENSETR        0x24
  53 #define SYSCFG_PMCCLRR          0x44
  54
  55 #define SYSCFG_BOOTR_BOOT_MASK          GENMASK(2, 0)
  56 #define SYSCFG_BOOTR_BOOTPD_SHIFT       4
  57
  58 #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE          BIT(0)
  59 #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI        BIT(1)
  60 #define SYSCFG_IOCTRLSETR_HSLVEN_ETH            BIT(2)
  61 #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC          BIT(3)
  62 #define SYSCFG_IOCTRLSETR_HSLVEN_SPI            BIT(4)
  63
  64 #define SYSCFG_CMPCR_SW_CTRL            BIT(1)
  65 #define SYSCFG_CMPCR_READY              BIT(8)
  66
  67 #define SYSCFG_CMPENSETR_MPU_EN         BIT(0)
  68
  69 #define SYSCFG_PMCSETR_ETH_CLK_SEL      BIT(16)
  70 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL  BIT(17)
  71
  72 #define SYSCFG_PMCSETR_ETH_SELMII       BIT(20)
  73
  74 #define SYSCFG_PMCSETR_ETH_SEL_MASK     GENMASK(23, 21)
  75 #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
  76 #define SYSCFG_PMCSETR_ETH_SEL_RGMII    BIT(21)
  77 #define SYSCFG_PMCSETR_ETH_SEL_RMII     BIT(23)
  78
  79 /*
  80  * Get a global data pointer
  81  */
  82 DECLARE_GLOBAL_DATA_PTR;
  83
  84 int setup_mac_address(void)
  85 {
  86         unsigned char enetaddr[6];
  87         struct udevice *dev;
  88         int off, ret;
  89
  90         ret = eth_env_get_enetaddr("ethaddr", enetaddr);
  91         if (ret)        /* ethaddr is already set */
  92                 return 0;
  93
  94         off = fdt_path_offset(gd->fdt_blob, "eeprom0");
  95         if (off < 0) {
  96                 printf("%s: No eeprom0 path offset\n", __func__);
  97                 return off;
  98         }
  99
 100         ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
 101         if (ret) {
 102                 printf("Cannot find EEPROM!\n");
 103                 return ret;
 104         }
 105
 106         ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
 107         if (ret) {
 108                 printf("Error reading configuration EEPROM!\n");
 109                 return ret;
 110         }
 111
 112         if (is_valid_ethaddr(enetaddr))
 113                 eth_env_set_enetaddr("ethaddr", enetaddr);
 114
 115         return 0;
 116 }
 117
 118 int checkboard(void)
 119 {
 120         char *mode;
 121         const char *fdt_compat;
 122         int fdt_compat_len;
 123
 124         if (IS_ENABLED(CONFIG_TFABOOT))
 125                 mode = "trusted";
 126         else
 127                 mode = "basic";
 128
 129         printf("Board: stm32mp1 in %s mode", mode);
 130         fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
 131                                  &fdt_compat_len);
 132         if (fdt_compat && fdt_compat_len)
 133                 printf(" (%s)", fdt_compat);
 134         puts("\n");
 135
 136         return 0;
 137 }
 138
 139 #ifdef CONFIG_BOARD_EARLY_INIT_F
 140 static u8 brdcode __section("data");
 141 static u8 ddr3code __section("data");
 142 static u8 somcode __section("data");
 143 static u32 opp_voltage_mv __section(".data");
 144
 145 static void board_get_coding_straps(void)
 146 {
 147         struct gpio_desc gpio[4];
 148         ofnode node;
 149         int i, ret;
 150
 151         node = ofnode_path("/config");
 152         if (!ofnode_valid(node)) {
 153                 printf("%s: no /config node?\n", __func__);
 154                 return;
 155         }
 156
 157         brdcode = 0;
 158         ddr3code = 0;
 159         somcode = 0;
 160
 161         ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
 162                                               gpio, ARRAY_SIZE(gpio),
 163                                               GPIOD_IS_IN);
 164         for (i = 0; i < ret; i++)
 165                 somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
 166
 167         ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
 168                                               gpio, ARRAY_SIZE(gpio),
 169                                               GPIOD_IS_IN);
 170         for (i = 0; i < ret; i++)
 171                 ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
 172
 173         ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
 174                                               gpio, ARRAY_SIZE(gpio),
 175                                               GPIOD_IS_IN);
 176         for (i = 0; i < ret; i++)
 177                 brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
 178
 179         printf("Code:  SoM:rev=%d,ddr3=%d Board:rev=%d\n",
 180                 somcode, ddr3code, brdcode);
 181 }
 182
 183 int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
 184                                          const char *name)
 185 {
 186         if (ddr3code == 1 &&
 187             !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz"))
 188                 return 0;
 189
 190         if (ddr3code == 2 &&
 191             !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz"))
 192                 return 0;
 193
 194         if (ddr3code == 3 &&
 195             !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz"))
 196                 return 0;
 197
 198         return -EINVAL;
 199 }
 200
 201 void board_vddcore_init(u32 voltage_mv)
 202 {
 203         if (IS_ENABLED(CONFIG_SPL_BUILD))
 204                 opp_voltage_mv = voltage_mv;
 205 }
 206
 207 int board_early_init_f(void)
 208 {
 209         if (IS_ENABLED(CONFIG_SPL_BUILD))
 210                 stpmic1_init(opp_voltage_mv);
 211         board_get_coding_straps();
 212
 213         return 0;
 214 }
 215
 216 #ifdef CONFIG_SPL_LOAD_FIT
 217 int board_fit_config_name_match(const char *name)
 218 {
 219         char test[20];
 220
 221         snprintf(test, sizeof(test), "somrev%d_boardrev%d", somcode, brdcode);
 222
 223         if (!strcmp(name, test))
 224                 return 0;
 225
 226         return -EINVAL;
 227 }
 228 #endif
 229 #endif
 230
 231 static void board_key_check(void)
 232 {
 233 #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
 234         ofnode node;
 235         struct gpio_desc gpio;
 236         enum forced_boot_mode boot_mode = BOOT_NORMAL;
 237
 238         node = ofnode_path("/config");
 239         if (!ofnode_valid(node)) {
 240                 debug("%s: no /config node?\n", __func__);
 241                 return;
 242         }
 243 #ifdef CONFIG_FASTBOOT
 244         if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
 245                                        &gpio, GPIOD_IS_IN)) {
 246                 debug("%s: could not find a /config/st,fastboot-gpios\n",
 247                       __func__);
 248         } else {
 249                 if (dm_gpio_get_value(&gpio)) {
 250                         puts("Fastboot key pressed, ");
 251                         boot_mode = BOOT_FASTBOOT;
 252                 }
 253
 254                 dm_gpio_free(NULL, &gpio);
 255         }
 256 #endif
 257 #ifdef CONFIG_CMD_STM32PROG
 258         if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
 259                                        &gpio, GPIOD_IS_IN)) {
 260                 debug("%s: could not find a /config/st,stm32prog-gpios\n",
 261                       __func__);
 262         } else {
 263                 if (dm_gpio_get_value(&gpio)) {
 264                         puts("STM32Programmer key pressed, ");
 265                         boot_mode = BOOT_STM32PROG;
 266                 }
 267                 dm_gpio_free(NULL, &gpio);
 268         }
 269 #endif
 270
 271         if (boot_mode != BOOT_NORMAL) {
 272                 puts("entering download mode...\n");
 273                 clrsetbits_le32(TAMP_BOOT_CONTEXT,
 274                                 TAMP_BOOT_FORCED_MASK,
 275                                 boot_mode);
 276         }
 277 #endif
 278 }
 279
 280 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
 281
 282 #include <usb/dwc2_udc.h>
 283 int g_dnl_board_usb_cable_connected(void)
 284 {
 285         struct udevice *dwc2_udc_otg;
 286         int ret;
 287
 288         ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
 289                                           DM_GET_DRIVER(dwc2_udc_otg),
 290                                           &dwc2_udc_otg);
 291         if (!ret)
 292                 debug("dwc2_udc_otg init failed\n");
 293
 294         return dwc2_udc_B_session_valid(dwc2_udc_otg);
 295 }
 296
 297 #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
 298 #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
 299
 300 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
 301 {
 302         if (!strcmp(name, "usb_dnl_dfu"))
 303                 put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
 304         else if (!strcmp(name, "usb_dnl_fastboot"))
 305                 put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
 306                               &dev->idProduct);
 307         else
 308                 put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
 309
 310         return 0;
 311 }
 312
 313 #endif /* CONFIG_USB_GADGET */
 314
 315 #ifdef CONFIG_LED
 316 static int get_led(struct udevice **dev, char *led_string)
 317 {
 318         char *led_name;
 319         int ret;
 320
 321         led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
 322         if (!led_name) {
 323                 pr_debug("%s: could not find %s config string\n",
 324                          __func__, led_string);
 325                 return -ENOENT;
 326         }
 327         ret = led_get_by_label(led_name, dev);
 328         if (ret) {
 329                 debug("%s: get=%d\n", __func__, ret);
 330                 return ret;
 331         }
 332
 333         return 0;
 334 }
 335
 336 static int setup_led(enum led_state_t cmd)
 337 {
 338         struct udevice *dev;
 339         int ret;
 340
 341         ret = get_led(&dev, "u-boot,boot-led");
 342         if (ret)
 343                 return ret;
 344
 345         ret = led_set_state(dev, cmd);
 346         return ret;
 347 }
 348 #endif
 349
 350 static void __maybe_unused led_error_blink(u32 nb_blink)
 351 {
 352 #ifdef CONFIG_LED
 353         int ret;
 354         struct udevice *led;
 355         u32 i;
 356 #endif
 357
 358         if (!nb_blink)
 359                 return;
 360
 361 #ifdef CONFIG_LED
 362         ret = get_led(&led, "u-boot,error-led");
 363         if (!ret) {
 364                 /* make u-boot,error-led blinking */
 365                 /* if U32_MAX and 125ms interval, for 17.02 years */
 366                 for (i = 0; i < 2 * nb_blink; i++) {
 367                         led_set_state(led, LEDST_TOGGLE);
 368                         mdelay(125);
 369                         WATCHDOG_RESET();
 370                 }
 371         }
 372 #endif
 373
 374         /* infinite: the boot process must be stopped */
 375         if (nb_blink == U32_MAX)
 376                 hang();
 377 }
 378
 379 static void sysconf_init(void)
 380 {
 381 #ifndef CONFIG_TFABOOT
 382         u8 *syscfg;
 383 #ifdef CONFIG_DM_REGULATOR
 384         struct udevice *pwr_dev;
 385         struct udevice *pwr_reg;
 386         struct udevice *dev;
 387         int ret;
 388         u32 otp = 0;
 389 #endif
 390         u32 bootr;
 391
 392         syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
 393
 394         /* interconnect update : select master using the port 1 */
 395         /* LTDC = AXI_M9 */
 396         /* GPU  = AXI_M8 */
 397         /* today information is hardcoded in U-Boot */
 398         writel(BIT(9), syscfg + SYSCFG_ICNR);
 399
 400         /* disable Pull-Down for boot pin connected to VDD */
 401         bootr = readl(syscfg + SYSCFG_BOOTR);
 402         bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
 403         bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
 404         writel(bootr, syscfg + SYSCFG_BOOTR);
 405
 406 #ifdef CONFIG_DM_REGULATOR
 407         /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
 408          * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
 409          * The customer will have to disable this for low frequencies
 410          * or if AFMUX is selected but the function not used, typically for
 411          * TRACE. Otherwise, impact on power consumption.
 412          *
 413          * WARNING:
 414          *   enabling High Speed mode while VDD>2.7V
 415          *   with the OTP product_below_2v5 (OTP 18, BIT 13)
 416          *   erroneously set to 1 can damage the IC!
 417          *   => U-Boot set the register only if VDD < 2.7V (in DT)
 418          *      but this value need to be consistent with board design
 419          */
 420         ret = uclass_get_device_by_driver(UCLASS_PMIC,
 421                                           DM_GET_DRIVER(stm32mp_pwr_pmic),
 422                                           &pwr_dev);
 423         if (!ret) {
 424                 ret = uclass_get_device_by_driver(UCLASS_MISC,
 425                                                   DM_GET_DRIVER(stm32mp_bsec),
 426                                                   &dev);
 427                 if (ret) {
 428                         pr_err("Can't find stm32mp_bsec driver\n");
 429                         return;
 430                 }
 431
 432                 ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
 433                 if (ret > 0)
 434                         otp = otp & BIT(13);
 435
 436                 /* get VDD = vdd-supply */
 437                 ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
 438                                                   &pwr_reg);
 439
 440                 /* check if VDD is Low Voltage */
 441                 if (!ret) {
 442                         if (regulator_get_value(pwr_reg) < 2700000) {
 443                                 writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
 444                                        SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
 445                                        SYSCFG_IOCTRLSETR_HSLVEN_ETH |
 446                                        SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
 447                                        SYSCFG_IOCTRLSETR_HSLVEN_SPI,
 448                                        syscfg + SYSCFG_IOCTRLSETR);
 449
 450                                 if (!otp)
 451                                         pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
 452                         } else {
 453                                 if (otp)
 454                                         pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
 455                         }
 456                 } else {
 457                         debug("VDD unknown");
 458                 }
 459         }
 460 #endif
 461
 462         /* activate automatic I/O compensation
 463          * warning: need to ensure CSI enabled and ready in clock driver
 464          */
 465         writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
 466
 467         while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
 468                 ;
 469         clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
 470 #endif
 471 }
 472
 473 static void board_init_fmc2(void)
 474 {
 475 #define STM32_FMC2_BCR1                 0x0
 476 #define STM32_FMC2_BTR1                 0x4
 477 #define STM32_FMC2_BWTR1                0x104
 478 #define STM32_FMC2_BCR(x)               ((x) * 0x8 + STM32_FMC2_BCR1)
 479 #define STM32_FMC2_BCRx_FMCEN           BIT(31)
 480 #define STM32_FMC2_BCRx_WREN            BIT(12)
 481 #define STM32_FMC2_BCRx_RSVD            BIT(7)
 482 #define STM32_FMC2_BCRx_FACCEN          BIT(6)
 483 #define STM32_FMC2_BCRx_MWID(n)         ((n) << 4)
 484 #define STM32_FMC2_BCRx_MTYP(n)         ((n) << 2)
 485 #define STM32_FMC2_BCRx_MUXEN           BIT(1)
 486 #define STM32_FMC2_BCRx_MBKEN           BIT(0)
 487 #define STM32_FMC2_BTR(x)               ((x) * 0x8 + STM32_FMC2_BTR1)
 488 #define STM32_FMC2_BTRx_DATAHLD(n)      ((n) << 30)
 489 #define STM32_FMC2_BTRx_BUSTURN(n)      ((n) << 16)
 490 #define STM32_FMC2_BTRx_DATAST(n)       ((n) << 8)
 491 #define STM32_FMC2_BTRx_ADDHLD(n)       ((n) << 4)
 492 #define STM32_FMC2_BTRx_ADDSET(n)       ((n) << 0)
 493
 494 #define RCC_MP_AHB6RSTCLRR              0x218
 495 #define RCC_MP_AHB6RSTCLRR_FMCRST       BIT(12)
 496 #define RCC_MP_AHB6ENSETR               0x19c
 497 #define RCC_MP_AHB6ENSETR_FMCEN         BIT(12)
 498
 499         const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
 500                         STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
 501                         STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
 502                         STM32_FMC2_BCRx_MBKEN;
 503         const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
 504                         STM32_FMC2_BTRx_BUSTURN(2) |
 505                         STM32_FMC2_BTRx_DATAST(0x22) |
 506                         STM32_FMC2_BTRx_ADDHLD(2) |
 507                         STM32_FMC2_BTRx_ADDSET(2);
 508
 509         /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
 510         writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
 511         writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
 512
 513         /* KS8851-16MLL -- Muxed mode */
 514         writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
 515         writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
 516         /* AS7C34098 SRAM on X11 -- Muxed mode */
 517         writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
 518         writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
 519
 520         setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
 521 }
 522
 523 /* board dependent setup after realloc */
 524 int board_init(void)
 525 {
 526         /* address of boot parameters */
 527         gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
 528
 529         if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
 530                 gpio_hog_probe_all();
 531
 532         board_key_check();
 533
 534 #ifdef CONFIG_DM_REGULATOR
 535         regulators_enable_boot_on(_DEBUG);
 536 #endif
 537
 538         sysconf_init();
 539
 540         board_init_fmc2();
 541
 542         if (CONFIG_IS_ENABLED(LED))
 543                 led_default_state();
 544
 545         return 0;
 546 }
 547
 548 int board_late_init(void)
 549 {
 550         char *boot_device;
 551 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 552         const void *fdt_compat;
 553         int fdt_compat_len;
 554
 555         fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
 556                                  &fdt_compat_len);
 557         if (fdt_compat && fdt_compat_len) {
 558                 if (strncmp(fdt_compat, "st,", 3) != 0)
 559                         env_set("board_name", fdt_compat);
 560                 else
 561                         env_set("board_name", fdt_compat + 3);
 562         }
 563 #endif
 564
 565         /* Check the boot-source to disable bootdelay */
 566         boot_device = env_get("boot_device");
 567         if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
 568                 env_set("bootdelay", "0");
 569
 570 #ifdef CONFIG_BOARD_EARLY_INIT_F
 571         env_set_ulong("dh_som_rev", somcode);
 572         env_set_ulong("dh_board_rev", brdcode);
 573         env_set_ulong("dh_ddr3_code", ddr3code);
 574 #endif
 575
 576         return 0;
 577 }
 578
 579 void board_quiesce_devices(void)
 580 {
 581 #ifdef CONFIG_LED
 582         setup_led(LEDST_OFF);
 583 #endif
 584 }
 585
 586 /* eth init function : weak called in eqos driver */
 587 int board_interface_eth_init(struct udevice *dev,
 588                              phy_interface_t interface_type)
 589 {
 590         u8 *syscfg;
 591         u32 value;
 592         bool eth_clk_sel_reg = false;
 593         bool eth_ref_clk_sel_reg = false;
 594
 595         /* Gigabit Ethernet 125MHz clock selection. */
 596         eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
 597
 598         /* Ethernet 50Mhz RMII clock selection */
 599         eth_ref_clk_sel_reg =
 600                 dev_read_bool(dev, "st,eth_ref_clk_sel");
 601
 602         syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
 603
 604         if (!syscfg)
 605                 return -ENODEV;
 606
 607         switch (interface_type) {
 608         case PHY_INTERFACE_MODE_MII:
 609                 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
 610                         SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
 611                 debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
 612                 break;
 613         case PHY_INTERFACE_MODE_GMII:
 614                 if (eth_clk_sel_reg)
 615                         value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
 616                                 SYSCFG_PMCSETR_ETH_CLK_SEL;
 617                 else
 618                         value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
 619                 debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
 620                 break;
 621         case PHY_INTERFACE_MODE_RMII:
 622                 if (eth_ref_clk_sel_reg)
 623                         value = SYSCFG_PMCSETR_ETH_SEL_RMII |
 624                                 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
 625                 else
 626                         value = SYSCFG_PMCSETR_ETH_SEL_RMII;
 627                 debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
 628                 break;
 629         case PHY_INTERFACE_MODE_RGMII:
 630         case PHY_INTERFACE_MODE_RGMII_ID:
 631         case PHY_INTERFACE_MODE_RGMII_RXID:
 632         case PHY_INTERFACE_MODE_RGMII_TXID:
 633                 if (eth_clk_sel_reg)
 634                         value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
 635                                 SYSCFG_PMCSETR_ETH_CLK_SEL;
 636                 else
 637                         value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
 638                 debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
 639                 break;
 640         default:
 641                 debug("%s: Do not manage %d interface\n",
 642                       __func__, interface_type);
 643                 /* Do not manage others interfaces */
 644                 return -EINVAL;
 645         }
 646
 647         /* clear and set ETH configuration bits */
 648         writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
 649                SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
 650                syscfg + SYSCFG_PMCCLRR);
 651         writel(value, syscfg + SYSCFG_PMCSETR);
 652
 653         return 0;
 654 }
 655
 656 enum env_location env_get_location(enum env_operation op, int prio)
 657 {
 658         if (prio)
 659                 return ENVL_UNKNOWN;
 660
 661 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
 662         return ENVL_SPI_FLASH;
 663 #else
 664         return ENVL_NOWHERE;
 665 #endif
 666 }
 667
 668 #if defined(CONFIG_OF_BOARD_SETUP)
 669 int ft_board_setup(void *blob, bd_t *bd)
 670 {
 671         return 0;
 672 }
 673 #endif
 674
 675 static void board_copro_image_process(ulong fw_image, size_t fw_size)
 676 {
 677         int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
 678
 679         if (!rproc_is_initialized())
 680                 if (rproc_init()) {
 681                         printf("Remote Processor %d initialization failed\n",
 682                                id);
 683                         return;
 684                 }
 685
 686         ret = rproc_load(id, fw_image, fw_size);
 687         printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
 688                id, fw_image, fw_size, ret ? " Failed!" : " Success!");
 689
 690         if (!ret) {
 691                 rproc_start(id);
 692                 env_set("copro_state", "booted");
 693         }
 694 }
 695
 696 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);