1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
10 #include <asm/arch/stm32.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/global_data.h>
19 #include <dm/device.h>
20 #include <dm/uclass.h>
22 #include <env_internal.h>
24 #include <generic-phy.h>
27 #include <i2c_eeprom.h>
36 #include <linux/bitops.h>
37 #include <linux/delay.h>
38 #include <power/regulator.h>
39 #include <remoteproc.h>
43 #include <usb/dwc2_udc.h>
45 #include <dm/ofnode.h>
46 #include "../../st/common/stpmic1.h"
48 /* SYSCFG registers */
49 #define SYSCFG_BOOTR 0x00
50 #define SYSCFG_PMCSETR 0x04
51 #define SYSCFG_IOCTRLSETR 0x18
52 #define SYSCFG_ICNR 0x1C
53 #define SYSCFG_CMPCR 0x20
54 #define SYSCFG_CMPENSETR 0x24
55 #define SYSCFG_PMCCLRR 0x44
57 #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
58 #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
60 #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
61 #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
62 #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
63 #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
64 #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
66 #define SYSCFG_CMPCR_SW_CTRL BIT(1)
67 #define SYSCFG_CMPCR_READY BIT(8)
69 #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
71 #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
72 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
74 #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
76 #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
77 #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
78 #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
79 #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
82 * Get a global data pointer
84 DECLARE_GLOBAL_DATA_PTR;
87 #define KS_CCR_EEPROM BIT(9)
88 #define KS_BE0 BIT(12)
89 #define KS_BE1 BIT(13)
91 #define CIDER_ID 0x8870
93 int setup_mac_address(void)
95 unsigned char enetaddr[6];
96 bool skip_eth0 = false;
97 bool skip_eth1 = false;
101 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
102 if (ret) /* ethaddr is already set */
105 off = fdt_path_offset(gd->fdt_blob, "ethernet1");
107 /* ethernet1 is not present in the system */
109 goto out_set_ethaddr;
112 ret = eth_env_get_enetaddr("eth1addr", enetaddr);
114 /* eth1addr is already set */
116 goto out_set_ethaddr;
119 ret = fdt_node_check_compatible(gd->fdt_blob, off, "micrel,ks8851-mll");
121 goto out_set_ethaddr;
124 * KS8851 with EEPROM may use custom MAC from EEPROM, read
125 * out the KS8851 CCR register to determine whether EEPROM
126 * is present. If EEPROM is present, it must contain valid
130 reg = fdt_get_base_address(gd->fdt_blob, off);
132 goto out_set_ethaddr;
134 writew(KS_BE0 | KS_BE1 | KS_CIDER, reg + 2);
136 if ((cider & 0xfff0) != CIDER_ID) {
138 goto out_set_ethaddr;
141 writew(KS_BE0 | KS_BE1 | KS_CCR, reg + 2);
143 if (ccr & KS_CCR_EEPROM) {
145 goto out_set_ethaddr;
149 if (skip_eth0 && skip_eth1)
152 off = fdt_path_offset(gd->fdt_blob, "eeprom0");
154 printf("%s: No eeprom0 path offset\n", __func__);
158 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
160 printf("Cannot find EEPROM!\n");
164 ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
166 printf("Error reading configuration EEPROM!\n");
170 if (is_valid_ethaddr(enetaddr)) {
172 eth_env_set_enetaddr("ethaddr", enetaddr);
176 eth_env_set_enetaddr("eth1addr", enetaddr);
185 const char *fdt_compat;
188 if (IS_ENABLED(CONFIG_TFABOOT))
193 printf("Board: stm32mp1 in %s mode", mode);
194 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
196 if (fdt_compat && fdt_compat_len)
197 printf(" (%s)", fdt_compat);
203 #ifdef CONFIG_BOARD_EARLY_INIT_F
204 static u8 brdcode __section("data");
205 static u8 ddr3code __section("data");
206 static u8 somcode __section("data");
207 static u32 opp_voltage_mv __section(".data");
209 static void board_get_coding_straps(void)
211 struct gpio_desc gpio[4];
215 node = ofnode_path("/config");
216 if (!ofnode_valid(node)) {
217 printf("%s: no /config node?\n", __func__);
225 ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
226 gpio, ARRAY_SIZE(gpio),
228 for (i = 0; i < ret; i++)
229 somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
231 ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
232 gpio, ARRAY_SIZE(gpio),
234 for (i = 0; i < ret; i++)
235 ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
237 ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
238 gpio, ARRAY_SIZE(gpio),
240 for (i = 0; i < ret; i++)
241 brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
243 printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
244 somcode, ddr3code, brdcode);
247 int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
251 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz"))
255 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz"))
259 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz"))
265 void board_vddcore_init(u32 voltage_mv)
267 if (IS_ENABLED(CONFIG_SPL_BUILD))
268 opp_voltage_mv = voltage_mv;
271 int board_early_init_f(void)
273 if (IS_ENABLED(CONFIG_SPL_BUILD))
274 stpmic1_init(opp_voltage_mv);
275 board_get_coding_straps();
280 #ifdef CONFIG_SPL_LOAD_FIT
281 int board_fit_config_name_match(const char *name)
286 compat = fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
288 snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d",
289 compat, somcode, brdcode);
291 if (!strcmp(name, test))
299 static void board_key_check(void)
301 #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
303 struct gpio_desc gpio;
304 enum forced_boot_mode boot_mode = BOOT_NORMAL;
306 node = ofnode_path("/config");
307 if (!ofnode_valid(node)) {
308 debug("%s: no /config node?\n", __func__);
311 #ifdef CONFIG_FASTBOOT
312 if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
313 &gpio, GPIOD_IS_IN)) {
314 debug("%s: could not find a /config/st,fastboot-gpios\n",
317 if (dm_gpio_get_value(&gpio)) {
318 puts("Fastboot key pressed, ");
319 boot_mode = BOOT_FASTBOOT;
322 dm_gpio_free(NULL, &gpio);
325 #ifdef CONFIG_CMD_STM32PROG
326 if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
327 &gpio, GPIOD_IS_IN)) {
328 debug("%s: could not find a /config/st,stm32prog-gpios\n",
331 if (dm_gpio_get_value(&gpio)) {
332 puts("STM32Programmer key pressed, ");
333 boot_mode = BOOT_STM32PROG;
335 dm_gpio_free(NULL, &gpio);
339 if (boot_mode != BOOT_NORMAL) {
340 puts("entering download mode...\n");
341 clrsetbits_le32(TAMP_BOOT_CONTEXT,
342 TAMP_BOOT_FORCED_MASK,
348 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
350 #include <usb/dwc2_udc.h>
351 int g_dnl_board_usb_cable_connected(void)
353 struct udevice *dwc2_udc_otg;
356 ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
357 DM_DRIVER_GET(dwc2_udc_otg),
360 debug("dwc2_udc_otg init failed\n");
362 return dwc2_udc_B_session_valid(dwc2_udc_otg);
365 #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
366 #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
368 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
370 if (!strcmp(name, "usb_dnl_dfu"))
371 put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
372 else if (!strcmp(name, "usb_dnl_fastboot"))
373 put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
376 put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
381 #endif /* CONFIG_USB_GADGET */
384 static int get_led(struct udevice **dev, char *led_string)
386 const char *led_name;
389 led_name = ofnode_conf_read_str(led_string);
391 pr_debug("%s: could not find %s config string\n",
392 __func__, led_string);
395 ret = led_get_by_label(led_name, dev);
397 debug("%s: get=%d\n", __func__, ret);
404 static int setup_led(enum led_state_t cmd)
409 ret = get_led(&dev, "u-boot,boot-led");
413 ret = led_set_state(dev, cmd);
418 static void __maybe_unused led_error_blink(u32 nb_blink)
430 ret = get_led(&led, "u-boot,error-led");
432 /* make u-boot,error-led blinking */
433 /* if U32_MAX and 125ms interval, for 17.02 years */
434 for (i = 0; i < 2 * nb_blink; i++) {
435 led_set_state(led, LEDST_TOGGLE);
442 /* infinite: the boot process must be stopped */
443 if (nb_blink == U32_MAX)
447 static void sysconf_init(void)
449 #ifndef CONFIG_TFABOOT
451 #ifdef CONFIG_DM_REGULATOR
452 struct udevice *pwr_dev;
453 struct udevice *pwr_reg;
460 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
462 /* interconnect update : select master using the port 1 */
465 /* today information is hardcoded in U-Boot */
466 writel(BIT(9), syscfg + SYSCFG_ICNR);
468 /* disable Pull-Down for boot pin connected to VDD */
469 bootr = readl(syscfg + SYSCFG_BOOTR);
470 bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
471 bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
472 writel(bootr, syscfg + SYSCFG_BOOTR);
474 #ifdef CONFIG_DM_REGULATOR
475 /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
476 * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
477 * The customer will have to disable this for low frequencies
478 * or if AFMUX is selected but the function not used, typically for
479 * TRACE. Otherwise, impact on power consumption.
482 * enabling High Speed mode while VDD>2.7V
483 * with the OTP product_below_2v5 (OTP 18, BIT 13)
484 * erroneously set to 1 can damage the IC!
485 * => U-Boot set the register only if VDD < 2.7V (in DT)
486 * but this value need to be consistent with board design
488 ret = uclass_get_device_by_driver(UCLASS_PMIC,
489 DM_DRIVER_GET(stm32mp_pwr_pmic),
492 ret = uclass_get_device_by_driver(UCLASS_MISC,
493 DM_DRIVER_GET(stm32mp_bsec),
496 pr_err("Can't find stm32mp_bsec driver\n");
500 ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
504 /* get VDD = vdd-supply */
505 ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
508 /* check if VDD is Low Voltage */
510 if (regulator_get_value(pwr_reg) < 2700000) {
511 writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
512 SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
513 SYSCFG_IOCTRLSETR_HSLVEN_ETH |
514 SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
515 SYSCFG_IOCTRLSETR_HSLVEN_SPI,
516 syscfg + SYSCFG_IOCTRLSETR);
519 pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
522 pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
525 debug("VDD unknown");
530 /* activate automatic I/O compensation
531 * warning: need to ensure CSI enabled and ready in clock driver
533 writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
535 while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
537 clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
541 static void board_init_fmc2(void)
543 #define STM32_FMC2_BCR1 0x0
544 #define STM32_FMC2_BTR1 0x4
545 #define STM32_FMC2_BWTR1 0x104
546 #define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
547 #define STM32_FMC2_BCRx_FMCEN BIT(31)
548 #define STM32_FMC2_BCRx_WREN BIT(12)
549 #define STM32_FMC2_BCRx_RSVD BIT(7)
550 #define STM32_FMC2_BCRx_FACCEN BIT(6)
551 #define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
552 #define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
553 #define STM32_FMC2_BCRx_MUXEN BIT(1)
554 #define STM32_FMC2_BCRx_MBKEN BIT(0)
555 #define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
556 #define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
557 #define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
558 #define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
559 #define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
560 #define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
562 #define RCC_MP_AHB6RSTCLRR 0x218
563 #define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
564 #define RCC_MP_AHB6ENSETR 0x19c
565 #define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
567 const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
568 STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
569 STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
570 STM32_FMC2_BCRx_MBKEN;
571 const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
572 STM32_FMC2_BTRx_BUSTURN(2) |
573 STM32_FMC2_BTRx_DATAST(0x22) |
574 STM32_FMC2_BTRx_ADDHLD(2) |
575 STM32_FMC2_BTRx_ADDSET(2);
577 /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
578 writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
579 writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
581 /* KS8851-16MLL -- Muxed mode */
582 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
583 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
584 /* AS7C34098 SRAM on X11 -- Muxed mode */
585 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
586 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
588 setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
591 /* board dependent setup after realloc */
596 #ifdef CONFIG_DM_REGULATOR
597 regulators_enable_boot_on(_DEBUG);
604 if (CONFIG_IS_ENABLED(LED))
610 int board_late_init(void)
613 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
614 const void *fdt_compat;
617 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
619 if (fdt_compat && fdt_compat_len) {
620 if (strncmp(fdt_compat, "st,", 3) != 0)
621 env_set("board_name", fdt_compat);
623 env_set("board_name", fdt_compat + 3);
627 /* Check the boot-source to disable bootdelay */
628 boot_device = env_get("boot_device");
629 if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
630 env_set("bootdelay", "0");
632 #ifdef CONFIG_BOARD_EARLY_INIT_F
633 env_set_ulong("dh_som_rev", somcode);
634 env_set_ulong("dh_board_rev", brdcode);
635 env_set_ulong("dh_ddr3_code", ddr3code);
641 void board_quiesce_devices(void)
644 setup_led(LEDST_OFF);
648 /* eth init function : weak called in eqos driver */
649 int board_interface_eth_init(struct udevice *dev,
650 phy_interface_t interface_type)
654 bool eth_clk_sel_reg = false;
655 bool eth_ref_clk_sel_reg = false;
657 /* Gigabit Ethernet 125MHz clock selection. */
658 eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
660 /* Ethernet 50Mhz RMII clock selection */
661 eth_ref_clk_sel_reg =
662 dev_read_bool(dev, "st,eth-ref-clk-sel");
664 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
669 switch (interface_type) {
670 case PHY_INTERFACE_MODE_MII:
671 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
672 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
673 debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
675 case PHY_INTERFACE_MODE_GMII:
677 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
678 SYSCFG_PMCSETR_ETH_CLK_SEL;
680 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
681 debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
683 case PHY_INTERFACE_MODE_RMII:
684 if (eth_ref_clk_sel_reg)
685 value = SYSCFG_PMCSETR_ETH_SEL_RMII |
686 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
688 value = SYSCFG_PMCSETR_ETH_SEL_RMII;
689 debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
691 case PHY_INTERFACE_MODE_RGMII:
692 case PHY_INTERFACE_MODE_RGMII_ID:
693 case PHY_INTERFACE_MODE_RGMII_RXID:
694 case PHY_INTERFACE_MODE_RGMII_TXID:
696 value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
697 SYSCFG_PMCSETR_ETH_CLK_SEL;
699 value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
700 debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
703 debug("%s: Do not manage %d interface\n",
704 __func__, interface_type);
705 /* Do not manage others interfaces */
709 /* clear and set ETH configuration bits */
710 writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
711 SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
712 syscfg + SYSCFG_PMCCLRR);
713 writel(value, syscfg + SYSCFG_PMCSETR);
718 #if defined(CONFIG_OF_BOARD_SETUP)
719 int ft_board_setup(void *blob, struct bd_info *bd)
725 static void board_copro_image_process(ulong fw_image, size_t fw_size)
727 int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
729 if (!rproc_is_initialized())
731 printf("Remote Processor %d initialization failed\n",
736 ret = rproc_load(id, fw_image, fw_size);
737 printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
738 id, fw_image, fw_size, ret ? " Failed!" : " Success!");
742 env_set("copro_state", "booted");
746 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);