board/denx/m53evk/m53evk.c

   1 /*
   2  * DENX M53 module
   3  *
   4  * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/imx-regs.h>
  28 #include <asm/arch/mx5x_pins.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <asm/arch/crm_regs.h>
  31 #include <asm/arch/clock.h>
  32 #include <asm/arch/iomux.h>
  33 #include <asm/arch/spl.h>
  34 #include <asm/errno.h>
  35 #include <netdev.h>
  36 #include <i2c.h>
  37 #include <mmc.h>
  38 #include <spl.h>
  39 #include <fsl_esdhc.h>
  40 #include <asm/gpio.h>
  41 #include <usb/ehci-fsl.h>
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 int dram_init(void)
  46 {
  47         u32 size1, size2;
  48
  49         size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  50         size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  51
  52         gd->ram_size = size1 + size2;
  53
  54         return 0;
  55 }
  56 void dram_init_banksize(void)
  57 {
  58         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  59         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  60
  61         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  62         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  63 }
  64
  65 static void setup_iomux_uart(void)
  66 {
  67         mxc_request_iomux(MX53_PIN_ATA_BUFFER_EN, IOMUX_CONFIG_ALT3);
  68         mxc_request_iomux(MX53_PIN_ATA_DMARQ, IOMUX_CONFIG_ALT3);
  69
  70         mxc_iomux_set_pad(MX53_PIN_ATA_BUFFER_EN,
  71                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
  72                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  73                                 PAD_CTL_HYS_ENABLE);
  74         mxc_iomux_set_pad(MX53_PIN_ATA_DMARQ,
  75                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
  76                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  77                                 PAD_CTL_HYS_ENABLE);
  78
  79         mxc_iomux_set_input(MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
  80 }
  81
  82 #ifdef CONFIG_USB_EHCI_MX5
  83 int board_ehci_hcd_init(int port)
  84 {
  85         if (port == 0) {
  86                 /* USB OTG PWRON */
  87                 mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1);
  88                 mxc_iomux_set_pad(MX53_PIN_GPIO_4,
  89                                 PAD_CTL_PKE_ENABLE |
  90                                 PAD_CTL_100K_PD |
  91                                 PAD_CTL_DRV_HIGH
  92                                 );
  93                 gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_4), 0);
  94
  95                 /* USB OTG Over Current */
  96                 mxc_request_iomux(MX53_PIN_GPIO_18, IOMUX_CONFIG_ALT1);
  97                 mxc_iomux_set_input(MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT, 1);
  98         } else if (port == 1) {
  99                 /* USB Host PWRON */
 100                 mxc_request_iomux(MX53_PIN_GPIO_2, IOMUX_CONFIG_ALT1);
 101                 mxc_iomux_set_pad(MX53_PIN_GPIO_2,
 102                                 PAD_CTL_PKE_ENABLE |
 103                                 PAD_CTL_100K_PD |
 104                                 PAD_CTL_DRV_HIGH
 105                                 );
 106                 gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_2), 0);
 107
 108                 /* USB Host Over Current */
 109                 mxc_request_iomux(MX53_PIN_GPIO_3, IOMUX_CONFIG_ALT6);
 110                 mxc_iomux_set_input(MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT, 1);
 111         }
 112
 113         return 0;
 114 }
 115 #endif
 116
 117 static void setup_iomux_fec(void)
 118 {
 119         /* MDIO IOMUX */
 120         mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
 121         mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
 122
 123         /* FEC 0 IOMUX */
 124         mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
 125         mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
 126         mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
 127         mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
 128         mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
 129         mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
 130         mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
 131         mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
 132
 133         /* FEC 1 IOMUX */
 134         mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6); /* RXD3 */
 135         mxc_request_iomux(MX53_PIN_KEY_ROW0, IOMUX_CONFIG_ALT6); /* TX_ER */
 136         mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6); /* RX_CLK */
 137         mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6); /* COL */
 138         mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6); /* RXD2 */
 139         mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6); /* TXD2 */
 140         mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6); /* CRS */
 141         mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6);  /* TXD3 */
 142
 143         /* MDIO PADs */
 144         mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
 145                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 146                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 147                                 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
 148         mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
 149         mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
 150
 151         /* FEC 0 PADs */
 152         mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
 153                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 154         mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
 155                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 156         mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
 157                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 158         mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
 159         mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
 160                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 161         mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
 162                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 163         mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
 164         mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
 165
 166         /* FEC 1 PADs */
 167         mxc_iomux_set_pad(MX53_PIN_KEY_COL0,    /* RXD3 */
 168                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 169         mxc_iomux_set_pad(MX53_PIN_KEY_ROW0,    /* TX_ER */
 170                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 171         mxc_iomux_set_pad(MX53_PIN_KEY_COL1,    /* RX_CLK */
 172                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 173         mxc_iomux_set_pad(MX53_PIN_KEY_ROW1,    /* COL */
 174                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 175         mxc_iomux_set_pad(MX53_PIN_KEY_COL2,    /* RXD2 */
 176                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 177         mxc_iomux_set_pad(MX53_PIN_KEY_ROW2,    /* TXD2 */
 178                         PAD_CTL_DRV_HIGH);
 179         mxc_iomux_set_pad(MX53_PIN_KEY_COL3,    /* CRS */
 180                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 181         mxc_iomux_set_pad(MX53_PIN_GPIO_19,     /* TXD3 */
 182                         PAD_CTL_DRV_HIGH);
 183 }
 184
 185 #ifdef CONFIG_FSL_ESDHC
 186 struct fsl_esdhc_cfg esdhc_cfg = {
 187         MMC_SDHC1_BASE_ADDR,
 188 };
 189
 190 int board_mmc_getcd(struct mmc *mmc)
 191 {
 192         mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
 193         gpio_direction_input(IMX_GPIO_NR(1, 1));
 194
 195         return !gpio_get_value(IMX_GPIO_NR(1, 1));
 196 }
 197
 198 int board_mmc_init(bd_t *bis)
 199 {
 200         esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 201
 202         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 203         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 204         mxc_request_iomux(MX53_PIN_SD1_DATA0,
 205                                 IOMUX_CONFIG_ALT0);
 206         mxc_request_iomux(MX53_PIN_SD1_DATA1,
 207                                 IOMUX_CONFIG_ALT0);
 208         mxc_request_iomux(MX53_PIN_SD1_DATA2,
 209                                 IOMUX_CONFIG_ALT0);
 210         mxc_request_iomux(MX53_PIN_SD1_DATA3,
 211                                 IOMUX_CONFIG_ALT0);
 212         mxc_request_iomux(MX53_PIN_EIM_DA13,
 213                                 IOMUX_CONFIG_ALT1);
 214
 215         mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
 216                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 217                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 218                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 219         mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
 220                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 221                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 222                 PAD_CTL_DRV_HIGH);
 223         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
 224                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 225                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 226                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 227         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
 228                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 229                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 230                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 231         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
 232                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 233                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 234                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 235         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
 236                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 237                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 238                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 239
 240         /* GPIO 2_31 is SD power */
 241         mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
 242         gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
 243
 244         return fsl_esdhc_initialize(bis, &esdhc_cfg);
 245 }
 246 #endif
 247
 248 static void setup_iomux_i2c(void)
 249 {
 250         mxc_request_iomux(MX53_PIN_EIM_D16,
 251                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
 252         mxc_request_iomux(MX53_PIN_EIM_EB2,
 253                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
 254
 255         mxc_iomux_set_pad(MX53_PIN_EIM_D16,
 256                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 257                 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
 258                 PAD_CTL_PUE_PULL |
 259                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 260         mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
 261                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 262                 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
 263                 PAD_CTL_PUE_PULL |
 264                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 265
 266         mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT, 0x1);
 267         mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT, 0x1);
 268 }
 269
 270 static void setup_iomux_nand(void)
 271 {
 272         mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
 273         mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
 274         mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0);
 275         mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0);
 276         mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
 277         mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
 278         mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
 279         mxc_request_iomux(MX53_PIN_ATA_DATA0, IOMUX_CONFIG_ALT3);
 280         mxc_request_iomux(MX53_PIN_ATA_DATA1, IOMUX_CONFIG_ALT3);
 281         mxc_request_iomux(MX53_PIN_ATA_DATA2, IOMUX_CONFIG_ALT3);
 282         mxc_request_iomux(MX53_PIN_ATA_DATA3, IOMUX_CONFIG_ALT3);
 283         mxc_request_iomux(MX53_PIN_ATA_DATA4, IOMUX_CONFIG_ALT3);
 284         mxc_request_iomux(MX53_PIN_ATA_DATA5, IOMUX_CONFIG_ALT3);
 285         mxc_request_iomux(MX53_PIN_ATA_DATA6, IOMUX_CONFIG_ALT3);
 286         mxc_request_iomux(MX53_PIN_ATA_DATA7, IOMUX_CONFIG_ALT3);
 287
 288         mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH);
 289         mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH);
 290         mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH);
 291         mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH);
 292         mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PUE_PULL |
 293                         PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
 294         mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PUE_PULL |
 295                         PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
 296         mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH);
 297         mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, PAD_CTL_DRV_HIGH |
 298                         PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
 299         mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, PAD_CTL_DRV_HIGH |
 300                         PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
 301         mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, PAD_CTL_DRV_HIGH |
 302                         PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
 303         mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, PAD_CTL_DRV_HIGH |
 304                         PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
 305         mxc_iomux_set_pad(MX53_PIN_ATA_DATA4, PAD_CTL_DRV_HIGH |
 306                         PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
 307         mxc_iomux_set_pad(MX53_PIN_ATA_DATA5, PAD_CTL_DRV_HIGH |
 308                         PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
 309         mxc_iomux_set_pad(MX53_PIN_ATA_DATA6, PAD_CTL_DRV_HIGH |
 310                         PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
 311         mxc_iomux_set_pad(MX53_PIN_ATA_DATA7, PAD_CTL_DRV_HIGH |
 312                         PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
 313 }
 314
 315 static void m53_set_clock(void)
 316 {
 317         int ret;
 318         const uint32_t ref_clk = MXC_HCLK;
 319         const uint32_t dramclk = 400;
 320         uint32_t cpuclk;
 321
 322         mxc_request_iomux(MX53_PIN_GPIO_10, IOMUX_CONFIG_GPIO);
 323         mxc_iomux_set_pad(MX53_PIN_GPIO_10, PAD_CTL_DRV_HIGH |
 324                         PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
 325         gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_10));
 326
 327         /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
 328         cpuclk = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_10)) ? 1200 : 800;
 329
 330         ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
 331         if (ret)
 332                 printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
 333
 334         ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
 335         if (ret) {
 336                 printf("CPU:   Switch peripheral clock to %dMHz failed\n",
 337                         dramclk);
 338         }
 339
 340         ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
 341         if (ret)
 342                 printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
 343 }
 344
 345 static void m53_set_nand(void)
 346 {
 347         u32 i;
 348
 349         /* NAND flash is muxed on ATA pins */
 350         setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
 351
 352         /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
 353         for (i = 0x4; i < 0x94; i += 0x18) {
 354                 clrbits_le32(WEIM_BASE_ADDR + i,
 355                              WEIM_GCR2_MUX16_BYP_GRANT_MASK);
 356         }
 357
 358         mxc_set_clock(0, 33, MXC_NFC_CLK);
 359         enable_nfc_clk(1);
 360 }
 361
 362 int board_early_init_f(void)
 363 {
 364         setup_iomux_uart();
 365         setup_iomux_fec();
 366         setup_iomux_i2c();
 367         setup_iomux_nand();
 368
 369         m53_set_clock();
 370
 371         mxc_set_sata_internal_clock();
 372
 373         /* NAND clock @ 33MHz */
 374         m53_set_nand();
 375
 376         return 0;
 377 }
 378
 379 int board_init(void)
 380 {
 381         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 382
 383         return 0;
 384 }
 385
 386 int checkboard(void)
 387 {
 388         puts("Board: DENX M53EVK\n");
 389
 390         return 0;
 391 }
 392
 393 /*
 394  * NAND SPL
 395  */
 396 #ifdef CONFIG_SPL_BUILD
 397 void spl_board_init(void)
 398 {
 399         setup_iomux_nand();
 400         m53_set_clock();
 401         m53_set_nand();
 402 }
 403
 404 u32 spl_boot_device(void)
 405 {
 406         return BOOT_DEVICE_NAND;
 407 }
 408 #endif