2 * (C) Copyright 2006 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
26 #ifdef CONFIG_NEW_NAND_CODE
29 #include <asm/arch/pxa-regs.h>
32 * hardware specific access to control-lines
33 * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
35 static void delta_hwcontrol(struct mtd_info *mtdinfo, int cmd)
38 struct nand_chip *this = mtdinfo->priv;
39 ulong base = (ulong) this->IO_ADDR_W;
43 MACRO_NAND_CTL_SETCLE((unsigned long)base);
46 MACRO_NAND_CTL_CLRCLE((unsigned long)base);
49 MACRO_NAND_CTL_SETALE((unsigned long)base);
52 MACRO_NAND_CTL_CLRALE((unsigned long)base);
55 MACRO_NAND_ENABLE_CE((unsigned long)base);
58 MACRO_NAND_DISABLE_CE((unsigned long)base);
65 /* read device ready pin */
66 static int delta_device_ready(struct mtd_info *mtdinfo)
73 struct nand_chip *this = mtdinfo->priv;
76 /* use the base addr to find out which chip are we dealing with */
77 switch((ulong) this->IO_ADDR_W) {
79 rb_gpio_pin = CFG_NAND0_RDY;
82 rb_gpio_pin = CFG_NAND1_RDY;
84 default: /* this should never happen */
89 if (in32(GPIO0_IR) & rb_gpio_pin)
95 static u_char delta_read_byte(struct mtd_info *mtd)
97 /* struct nand_chip *this = mtd->priv; */
100 /* wait for read request */
102 if(NDSR & NDSR_RDDREQ) {
109 printk("delta_read_byte: 0x%x.\n", tmp);
113 /* this is really monahans, not board specific ... */
114 static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
115 int column, int page_addr)
117 /* register struct nand_chip *this = mtd->priv; */
118 unsigned long ndcb0=0, ndcb1=0, ndcb2=0;
124 /* apparently NDCR[NDRUN] needs to be set before writing to NDCBx */
127 /* wait for write command request
128 * hmm, might be nice if this could time-out. mk@tbd
131 if(NDSR & NDSR_WRCMDREQ) {
132 NDSR |= NDSR_WRCMDREQ; /* Ack */
137 /* if command is a double byte cmd, we set bit double cmd bit 19 */
138 command2 = (command>>8) & 0xFF;
139 ndcb0 = command | ((command2 ? 1 : 0) << 19);
142 case NAND_CMD_READID:
143 printk("delta_cmdfunc: NAND_CMD_READID.\n");
144 ndcb0 |= ((3 << 21) | (1 << 16)); /* addr cycles*/
146 case NAND_CMD_PAGEPROG:
147 case NAND_CMD_ERASE1:
148 case NAND_CMD_ERASE2:
150 case NAND_CMD_STATUS:
155 printk("delta_cmdfunc: error, unkown command issued.\n");
164 void delta_dfc_gpio_init()
166 printf("Setting up DFC GPIO's.\n");
168 /* no idea what is done here, see zylonite.c */
171 DF_ALE_WE1 = 0x00000001;
172 DF_ALE_WE2 = 0x00000001;
173 DF_nCS0 = 0x00000001;
174 DF_nCS1 = 0x00000001;
182 DF_IO10 = 0x00000001;
184 DF_IO11 = 0x00000001;
186 DF_IO12 = 0x00000001;
188 DF_IO13 = 0x00000001;
190 DF_IO14 = 0x00000001;
192 DF_IO15 = 0x00000001;
202 * Board-specific NAND initialization. The following members of the
203 * argument are board-specific (per include/linux/mtd/nand_new.h):
204 * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
205 * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
206 * - hwcontrol: hardwarespecific function for accesing control-lines
207 * - dev_ready: hardwarespecific function for accesing device ready/busy line
208 * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
209 * only be provided if a hardware ECC is available
210 * - eccmode: mode of ecc, see defines
211 * - chip_delay: chip dependent delay for transfering data from array to
213 * - options: various chip options. They can partly be set to inform
214 * nand_scan about special functionality. See the defines for further
216 * Members with a "?" were not set in the merged testing-NAND branch,
217 * so they are not set here either.
219 void board_nand_init(struct nand_chip *nand)
221 unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
223 /* set up GPIO Control Registers */
224 delta_dfc_gpio_init();
226 /* turn on the NAND Controller Clock (104 MHz @ D0) */
227 CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
229 /* NAND Timing Parameters (in ns) */
230 #define NAND_TIMING_tCH 10
231 #define NAND_TIMING_tCS 0
232 #define NAND_TIMING_tWH 20
233 #define NAND_TIMING_tWP 40
234 #define NAND_TIMING_tRH 20
235 #define NAND_TIMING_tRP 40
236 #define NAND_TIMING_tR 11123
237 #define NAND_TIMING_tWHR 110
238 #define NAND_TIMING_tAR 10
240 /* Maximum values for NAND Interface Timing Registers in DFC clock
242 #define DFC_MAX_tCH 7
243 #define DFC_MAX_tCS 7
244 #define DFC_MAX_tWH 7
245 #define DFC_MAX_tWP 7
246 #define DFC_MAX_tRH 7
247 #define DFC_MAX_tRP 15
248 #define DFC_MAX_tR 65535
249 #define DFC_MAX_tWHR 15
250 #define DFC_MAX_tAR 15
252 #define DFC_CLOCK 104 /* DFC Clock is 104 MHz */
253 #define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */
254 #define MIN(x, y) ((x < y) ? x : y)
257 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
259 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
261 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
263 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
265 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
267 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
269 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
271 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
273 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
277 /* tRP value is split in the register */
285 NDTR0CS0 = (tCH << 19) |
293 NDTR1CS0 = (tR << 16) |
299 /* If it doesn't work (unlikely) think about:
301 * - chip select don't care
302 * - read id byte count
304 * Intentionally enabled by not setting bits:
307 * - cs don't care, see if we can enable later!
308 * - row address start position (after second cycle)
309 * - pages per block = 32
311 NDCR = (NDCR_ND_ARB_EN | /* enable bus arbiter */
312 NDCR_SPARE_EN | /* use the spare area */
313 NDCR_DWIDTH_C | /* 16bit DFC data bus width */
314 NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
315 (2 << 16) | /* read id count = 7 ???? mk@tbd */
316 NDCE_RDYM | /* flash device ready ir masked */
317 NDCE_CS0_PAGEDM | /* ND_nCSx page done ir masked */
319 NDCE_CS0_CMDDM | /* ND_CSx command done ir masked */
321 NDCE_CS0_BBDM | /* ND_CSx bad block detect ir masked */
323 NDCE_DBERRM | /* double bit error ir masked */
324 NDCE_SBERRM | /* single bit error ir masked */
325 NDCE_WRDREQM | /* write data request ir masked */
326 NDCE_RDDREQM | /* read data request ir masked */
327 NDCE_WRCMDREQM); /* write command request ir masked */
331 nand->hwcontrol = delta_hwcontrol;
332 nand->dev_ready = delta_device_ready;
333 nand->eccmode = NAND_ECC_SOFT;
334 nand->chip_delay = NAND_DELAY_US;
335 nand->options = NAND_BUSWIDTH_16;
336 nand->read_byte = delta_read_byte;
337 nand->cmdfunc = delta_cmdfunc;
338 /* nand->options = NAND_SAMSUNG_LP_OPTIONS; */
342 #error "U-Boot legacy NAND support not available for delta board."