2 * (C) Copyright 2006 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
26 #ifdef CONFIG_NEW_NAND_CODE
29 #include <asm/arch/pxa-regs.h>
32 * not required for Monahans DFC
34 static void delta_hwcontrol(struct mtd_info *mtdinfo, int cmd)
39 /* read device ready pin */
40 static int delta_device_ready(struct mtd_info *mtdinfo)
50 * static void delta_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
52 * Shouldn't this be "u_char * const buf" ?
54 static void delta_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
59 if(NDSR & NDSR_RDDREQ) {
65 /* we have to be carefull not to overflow the buffer if len is
66 * not a multiple of 4 */
67 unsigned long num_words = len & 0xfffffffc;
68 unsigned long rest = len & 0x3;
70 /* if there are any, first copy multiple of 4 bytes */
72 for(i=0; i<num_words; i+=4) {
73 unsigned long *long_buf = &buf[i];
74 /* ((unsigned long *) &buf[i]) = NDDB; */
79 /* ...then the rest */
81 unsigned long rest_data = NDDB;
83 buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
89 /* global var, too bad */
90 static unsigned long read_buf = 0;
91 static unsigned char bytes_read = 0;
93 static u_char delta_read_byte(struct mtd_info *mtd)
95 /* struct nand_chip *this = mtd->priv; */
99 /* wait for read request */
101 if(NDSR & NDSR_RDDREQ) {
107 printk("delta_read_byte: 0x%x.\n", read_buf);
109 byte = (unsigned char) (read_buf>>(8 * bytes_read++));
113 printf("delta_read_byte: returning 0x%x.\n", byte);
117 /* this is really monahans, not board specific ... */
118 static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
119 int column, int page_addr)
121 /* register struct nand_chip *this = mtd->priv; */
122 unsigned long ndcb0=0, ndcb1=0, ndcb2=0;
124 /* clear the ugly byte read buffer */
131 /* apparently NDCR[NDRUN] needs to be set before writing to NDCBx */
134 /* wait for write command request
135 * hmm, might be nice if this could time-out. mk@tbd
138 if(NDSR & NDSR_WRCMDREQ) {
139 NDSR |= NDSR_WRCMDREQ; /* Ack */
144 /* if command is a double byte cmd, we set bit double cmd bit 19 */
145 /* command2 = (command>>8) & 0xFF; */
146 /* ndcb0 = command | ((command2 ? 1 : 0) << 19); *\/ */
150 ndcb0 = (NAND_CMD_READ0 | (4<<16));
151 column >>= 1; /* adjust for 16 bit bus */
152 ndcb1 = (((column>>1) & 0xff) |
153 ((page_addr<<8) & 0xff00) |
154 ((page_addr<<8) & 0xff0000) |
155 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
157 case NAND_CMD_READID:
158 printk("delta_cmdfunc: NAND_CMD_READID.\n");
159 ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
161 case NAND_CMD_PAGEPROG:
163 case NAND_CMD_ERASE1:
164 case NAND_CMD_ERASE2:
167 ndcb0 = (NAND_CMD_SEQIN<<8) | (1<<19) | (4<<16);
168 if(column >= mtd->oobblock) {
170 column -= mtd->oobblock;
171 ndcb0 |= NAND_CMD_READOOB;
172 } else if (column < 256) {
173 /* First 256 bytes --> READ0 */
174 ndcb0 |= NAND_CMD_READ0;
176 /* Only for 8 bit devices - not delta!!! */
178 ndcb0 |= NAND_CMD_READ1;
181 case NAND_CMD_STATUS:
186 printk("delta_cmdfunc: error, unsupported command.\n");
195 static void delta_dfc_gpio_init()
197 printf("Setting up DFC GPIO's.\n");
199 /* no idea what is done here, see zylonite.c */
202 DF_ALE_WE1 = 0x00000001;
203 DF_ALE_WE2 = 0x00000001;
204 DF_nCS0 = 0x00000001;
205 DF_nCS1 = 0x00000001;
213 DF_IO10 = 0x00000001;
215 DF_IO11 = 0x00000001;
217 DF_IO12 = 0x00000001;
219 DF_IO13 = 0x00000001;
221 DF_IO14 = 0x00000001;
223 DF_IO15 = 0x00000001;
233 * Board-specific NAND initialization. The following members of the
234 * argument are board-specific (per include/linux/mtd/nand_new.h):
235 * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
236 * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
237 * - hwcontrol: hardwarespecific function for accesing control-lines
238 * - dev_ready: hardwarespecific function for accesing device ready/busy line
239 * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
240 * only be provided if a hardware ECC is available
241 * - eccmode: mode of ecc, see defines
242 * - chip_delay: chip dependent delay for transfering data from array to
244 * - options: various chip options. They can partly be set to inform
245 * nand_scan about special functionality. See the defines for further
247 * Members with a "?" were not set in the merged testing-NAND branch,
248 * so they are not set here either.
250 void wait(unsigned long us)
252 #define OSCR_CLK_FREQ 3.250 /* kHz */
254 unsigned long start = OSCR;
255 unsigned long delta = 0, cur;
260 if(cur < start) /* OSCR overflowed */
261 delta = cur + (start^0xffffffff);
267 void board_nand_init(struct nand_chip *nand)
269 unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
271 /* set up GPIO Control Registers */
272 delta_dfc_gpio_init();
274 /* turn on the NAND Controller Clock (104 MHz @ D0) */
275 CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
278 /* printf("stupid loop start...\n"); */
280 /* printf("stupid loop end.\n"); */
283 /* NAND Timing Parameters (in ns) */
284 #define NAND_TIMING_tCH 10
285 #define NAND_TIMING_tCS 0
286 #define NAND_TIMING_tWH 20
287 #define NAND_TIMING_tWP 40
288 /* #define NAND_TIMING_tRH 20 */
289 /* #define NAND_TIMING_tRP 40 */
291 #define NAND_TIMING_tRH 25
292 #define NAND_TIMING_tRP 50
294 #define NAND_TIMING_tR 11123
295 #define NAND_TIMING_tWHR 110
296 #define NAND_TIMING_tAR 10
298 /* Maximum values for NAND Interface Timing Registers in DFC clock
300 #define DFC_MAX_tCH 7
301 #define DFC_MAX_tCS 7
302 #define DFC_MAX_tWH 7
303 #define DFC_MAX_tWP 7
304 #define DFC_MAX_tRH 7
305 #define DFC_MAX_tRP 15
306 #define DFC_MAX_tR 65535
307 #define DFC_MAX_tWHR 15
308 #define DFC_MAX_tAR 15
310 #define DFC_CLOCK 104 /* DFC Clock is 104 MHz */
311 #define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */
312 #define MIN(x, y) ((x < y) ? x : y)
315 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
317 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
319 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
321 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
323 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
325 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
327 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
329 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
331 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
335 printf("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
337 /* tRP value is split in the register */
345 NDTR0CS0 = (tCH << 19) |
353 NDTR1CS0 = (tR << 16) |
359 /* If it doesn't work (unlikely) think about:
361 * - chip select don't care
362 * - read id byte count
364 * Intentionally enabled by not setting bits:
367 * - cs don't care, see if we can enable later!
368 * - row address start position (after second cycle)
369 * - pages per block = 32
370 * - ND_RDY : clears command buffer
372 NDCR = (NDCR_SPARE_EN | /* use the spare area */
373 NDCR_DWIDTH_C | /* 16bit DFC data bus width */
374 NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
375 NDCR_NCSX | /* Chip select busy don't care */
376 (7 << 16) | /* read id count = 7 ???? mk@tbd */
377 NDCR_ND_ARB_EN | /* enable bus arbiter */
378 NDCR_RDYM | /* flash device ready ir masked */
379 NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
381 NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
383 NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
385 NDCR_DBERRM | /* double bit error ir masked */
386 NDCR_SBERRM | /* single bit error ir masked */
387 NDCR_WRDREQM | /* write data request ir masked */
388 NDCR_RDDREQM | /* read data request ir masked */
389 NDCR_WRCMDREQM); /* write command request ir masked */
392 /* wait 10 us due to cmd buffer clear reset */
396 nand->hwcontrol = delta_hwcontrol;
397 /* nand->dev_ready = delta_device_ready; */
398 nand->eccmode = NAND_ECC_SOFT;
399 nand->chip_delay = NAND_DELAY_US;
400 nand->options = NAND_BUSWIDTH_16;
401 nand->read_byte = delta_read_byte;
402 nand->read_buf = delta_read_buf;
403 nand->cmdfunc = delta_cmdfunc;
404 /* nand->options = NAND_SAMSUNG_LP_OPTIONS; */
408 #error "U-Boot legacy NAND support not available for delta board."