2 * Most of this taken from Redboot hal_platform_setup.h with cleanup
4 * NOTE: I haven't clean this up considerably, just enough to get it
5 * running. See hal_platform_setup.h for the source. See
6 * board/cradle/lowlevel_init.S for another PXA250 setup that is
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/pxa-regs.h>
32 DRAM_SIZE: .long CFG_DRAM_SIZE
34 /* wait for coprocessor write complete */
36 mrc p15,0,\reg,c2,c0,0
58 /* Set up GPIO pins first ----------------------------------------- */
61 /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */
70 /* tebrandt - ASCR, clear the RDH bit */
73 bic r1, r1, #0x80000000
76 /* ---------------------------------------------------------------- */
77 /* Enable memory interface */
78 /* ---------------------------------------------------------------- */
80 /* ---------------------------------------------------------------- */
81 /* Step 1: Wait for at least 200 microsedonds to allow internal */
82 /* clocks to settle. Only necessary after hard reset... */
83 /* FIXME: can be optimized later */
84 /* ---------------------------------------------------------------- */
89 #define NEW_SDRAM_INIT 1
92 /* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
99 /* 2. Programm MDCNFG, leaving DMCEN de-asserted */
101 ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
102 /* ldr r1, =0x80000403 */
104 ldr r1, [r0] /* delay until written */
106 /* 3. wait nop power up waiting period (200ms)
107 * optimization: Steps 4+6 can be done during this
111 /* 4. Perform an initial Rcomp-calibration cycle */
115 ldr r1, [r0] /* delay until written */
116 /* missing: program for automatic rcomp evaluation cycles */
118 /* 5. DDR DRAM strobe delay calibration */
123 ldr r1, [r0] /* delay until written */
131 /* Configure MDREFR */
137 /* Enable the dynamic memory controller */
140 orr r1, r1, #MDCNFG_DMCEN
144 #else /* NEW_SDRAM_INIT */
146 /* configure the MEMCLKCFG register */
150 ldr r2, [r1] @ DELAY UNTIL WRITTEN
152 /* set CSADRCFG[0] to data flash SRAM mode */
156 ldr r2, [r1] @ DELAY UNTIL WRITTEN
158 /* set CSADRCFG[1] to data flash SRAM mode */
162 ldr r2, [r1] @ DELAY UNTIL WRITTEN
164 /* set MSC 0 register for SRAM memory */
168 ldr r2, [r1] @ DELAY UNTIL WRITTEN
170 /* set CSADRCFG[2] to data flash SRAM mode */
174 ldr r2, [r1] @ DELAY UNTIL WRITTEN
176 /* set CSADRCFG[3] to VLIO mode */
180 ldr r2, [r1] @ DELAY UNTIL WRITTEN
182 /* set MSC 1 register for VLIO memory */
186 ldr r2, [r1] @ DELAY UNTIL WRITTEN
189 /* This does not work in Zylonite. -SC */
196 /* Configure ACCR Register */
202 /* Configure MDCNFG Register */
203 ldr r0, =MDCNFG @ MDCNFG
208 /* Perform Resistive Compensation by configuring RCOMP register */
209 ldr r1, =RCOMP @ RCOMP
214 /* Configure MDMRS Register for SDCS0 */
215 ldr r1, =MDMRS @ MDMRS
222 /* Configure MDMRS Register for SDCS1 */
223 ldr r1, =MDMRS @ MDMRS
230 /* Configure MDREFR */
231 ldr r1, =MDREFR @ MDREFR
242 /* Hardware DDR Read-Strobe Delay Calibration */
243 ldr r0, =DDR_HCAL @ DDR_HCAL
244 ldr r1, =0x803ffc07 @ the offset is correct? -SC
249 /* Here we assume the hardware calibration alwasy be successful. -SC */
250 /* Set DMCEN bit in MDCNFG Register */
251 ldr r0, =MDCNFG @ MDCNFG
253 orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
256 #endif /* NEW_SDRAM_INIT */
258 #ifndef CFG_SKIP_DRAM_SCRUB
259 /* scrub/init SDRAM if enabled/present */
260 ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */
261 ldr r9, =CFG_DRAM_SIZE /* size of memory to scrub (CFG_DRAM_SIZE) */
262 mov r0, #0 /* scrub with 0x0000:0000 */
270 10: /* fastScrubLoop */
271 subs r9, r9, #32 /* 8 words/line */
275 #endif /* CFG_SKIP_DRAM_SCRUB */
278 /* Mask all interrupts */
280 mcr p6, 0, r1, c1, c0, 0 @ ICMR
282 /* Disable software and data breakpoints */
284 mcr p15,0,r0,c14,c8,0 // ibcr0
285 mcr p15,0,r0,c14,c9,0 // ibcr1
286 mcr p15,0,r0,c14,c4,0 // dbcon
288 /* Enable all debug functionality */
290 mcr p14,0,r0,c10,c0,0 // dcsr
298 @********************************************************************************
301 @ This function is used to calibrate DQS delay lines.
302 @ Monahans supports three ways to do it. One is software
303 @ calibration. Two is hardware calibration. Three is hybrid
310 @ Case 1: Write the correct delay value once
311 @ Configure DDR_SCAL Register
312 ldr r0, =DDR_SCAL @ DDR_SCAL
313 q ldr r1, =0xaf2f2f2f
317 /* @ Case 2: Software Calibration
318 @ Write test pattern to memory
319 ldr r5, =0x0faf0faf @ Data Pattern
320 ldr r4, =0xa0000000 @ DDR ram
323 mov r1, =0x0 @ delay count
337 orr r3, r3, =0x80000000
356 orr r3, r3, =0x80000000
373 orr r3, r3, =0x80000000
378 @ Case 3: Hardware Calibratoin
379 ldr r0, =DDR_HCAL @ DDR_HCAL
380 ldr r1, =0x803ffc07 @ the offset is correct? -SC