1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Based on da850evm.c. Original Copyrights follow:
7 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
8 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
16 #include <asm/arch/hardware.h>
17 #include <asm/global_data.h>
18 #include <asm/ti-common/davinci_nand.h>
21 #include <dm/platdata.h>
22 #include <linux/errno.h>
23 #include <asm/mach-types.h>
24 #include <asm/arch/davinci_misc.h>
25 #ifdef CONFIG_MMC_DAVINCI
27 #include <asm/arch/sdmmc_defs.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
34 #ifdef CONFIG_MMC_DAVINCI
35 /* MMC0 pin muxer settings */
36 const struct pinmux_config mmc0_pins[] = {
37 /* GP0[11] is required for SD to work on Rev 3 EVMs */
38 { pinmux(0), 8, 4 }, /* GP0[11] */
39 { pinmux(10), 2, 0 }, /* MMCSD0_CLK */
40 { pinmux(10), 2, 1 }, /* MMCSD0_CMD */
41 { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
42 { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
43 { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
44 { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
45 /* LCDK supports only 4-bit mode, remaining pins are not configured */
49 /* UART pin muxer settings */
50 static const struct pinmux_config uart_pins[] = {
57 #ifdef CONFIG_DRIVER_TI_EMAC
58 static const struct pinmux_config emac_pins[] = {
77 #endif /* CONFIG_DRIVER_TI_EMAC */
79 /* I2C pin muxer settings */
80 static const struct pinmux_config i2c_pins[] = {
85 #ifdef CONFIG_NAND_DAVINCI
86 const struct pinmux_config nand_pins[] = {
107 { pinmux(12), 1, 5 },
113 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
119 const struct pinmux_resource pinmuxes[] = {
120 PINMUX_ITEM(uart_pins),
121 PINMUX_ITEM(i2c_pins),
122 #ifdef CONFIG_NAND_DAVINCI
123 PINMUX_ITEM(nand_pins),
127 const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
129 const struct lpsc_resource lpsc[] = {
130 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
131 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
132 { DAVINCI_LPSC_EMAC }, /* image download */
133 { DAVINCI_LPSC_UART2 }, /* console */
134 { DAVINCI_LPSC_GPIO },
135 #ifdef CONFIG_MMC_DAVINCI
136 { DAVINCI_LPSC_MMC_SD },
140 const int lpsc_size = ARRAY_SIZE(lpsc);
142 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
143 #define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000
147 * get_board_rev() - setup to pass kernel board revision information
149 * bit[0-3] Maximum cpu clock rate supported by onboard SoC
155 u32 get_board_rev(void)
160 int board_early_init_f(void)
163 * Power on required peripherals
164 * ARM does not have access by default to PSC0 and PSC1
165 * assuming here that the DSP bootloader has set the IOPU
166 * such that PSC access is available to ARM
168 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
178 /* arch number of the board */
179 gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
181 /* address of boot parameters */
182 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
185 /* setup the SUSPSRC for ARM to control emulation suspend */
186 writel(readl(&davinci_syscfg_regs->suspsrc) &
187 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
188 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
189 DAVINCI_SYSCFG_SUSPSRC_UART2),
190 &davinci_syscfg_regs->suspsrc);
192 /* configure pinmux settings */
193 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
196 #ifdef CONFIG_NAND_DAVINCI
198 * NAND CS setup - cycle counts based on da850evm NAND timings in the
199 * Linux kernel @ 25MHz EMIFA
201 writel((DAVINCI_ABCR_WSETUP(15) |
202 DAVINCI_ABCR_WSTROBE(63) |
203 DAVINCI_ABCR_WHOLD(7) |
204 DAVINCI_ABCR_RSETUP(15) |
205 DAVINCI_ABCR_RSTROBE(63) |
206 DAVINCI_ABCR_RHOLD(7) |
208 DAVINCI_ABCR_ASIZE_16BIT),
209 &davinci_emif_regs->ab2cr); /* CS3 */
213 #ifdef CONFIG_MMC_DAVINCI
214 if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
218 #ifdef CONFIG_DRIVER_TI_EMAC
219 if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
221 davinci_emac_mii_mode_sel(HAS_RMII);
222 #endif /* CONFIG_DRIVER_TI_EMAC */
224 /* enable the console UART */
225 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
226 DAVINCI_UART_PWREMU_MGMT_UTRST),
227 &davinci_uart2_ctrl_regs->pwremu_mgmt);
232 #define CFG_MAC_ADDR_SPI_BUS 0
233 #define CFG_MAC_ADDR_SPI_CS 0
234 #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
235 #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
237 #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
239 static int get_mac_addr(u8 *addr)
241 /* Need to find a way to get MAC ADDRESS */
245 void dsp_lpsc_on(unsigned domain, unsigned int id)
247 dv_reg_p mdstat, mdctl, ptstat, ptcmd;
248 struct davinci_psc_regs *psc_regs;
250 psc_regs = davinci_psc0_regs;
251 mdstat = &psc_regs->psc0.mdstat[id];
252 mdctl = &psc_regs->psc0.mdctl[id];
253 ptstat = &psc_regs->ptstat;
254 ptcmd = &psc_regs->ptcmd;
256 while (*ptstat & (0x1 << domain))
259 if ((*mdstat & 0x1f) == 0x03)
260 return; /* Already on and enabled */
264 *ptcmd = 0x1 << domain;
266 while (*ptstat & (0x1 << domain))
268 while ((*mdstat & 0x1f) != 0x03)
269 ; /* Probably an overkill... */
272 static void dspwake(void)
274 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
276 /* if the device is ARM only, return */
277 if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10)
280 if (!strcmp(env_get("dspwake"), "no"))
283 *resetvect++ = 0x1E000; /* DSP Idle */
284 /* clear out the next 10 words as NOP */
285 memset(resetvect, 0, sizeof(unsigned) * 10);
287 /* setup the DSP reset vector */
288 REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE;
290 dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
291 REG(PSC0_MDCTL + (15 * 4)) |= 0x100;
294 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
299 int rmii_hw_init(void)
303 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
305 int misc_init_r(void)
307 uint8_t tmp[20], addr[10];
310 if (env_get("ethaddr") == NULL) {
311 /* Read Ethernet MAC address from EEPROM */
312 if (dvevm_read_mac_address(addr)) {
313 /* Set Ethernet MAC address from EEPROM */
314 davinci_sync_env_enetaddr(addr);
319 if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) {
320 sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x",
321 addr[0], addr[1], addr[2], addr[3], addr[4],
324 env_set("ethaddr", (char *)tmp);
326 printf("Invalid MAC address read.\n");
330 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
331 /* Select RMII fucntion through the expander */
333 printf("RMII hardware init failed!!!\n");
341 #if !CONFIG_IS_ENABLED(DM_MMC)
342 #ifdef CONFIG_MMC_DAVINCI
343 static struct davinci_mmc mmc_sd0 = {
344 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
345 .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
346 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
349 int board_mmc_init(struct bd_info *bis)
351 mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
353 /* Add slot-0 to mmc subsystem */
354 return davinci_mmc_init(bis, &mmc_sd0);
359 #ifdef CONFIG_SPL_BUILD
360 static const struct ns16550_plat serial_pdata = {
361 .base = DAVINCI_UART2_BASE,
364 .fcr = UART_FCR_DEFVAL,
367 U_BOOT_DRVINFO(omapl138_uart) = {
368 .name = "ns16550_serial",
369 .plat = &serial_pdata,
372 static const struct davinci_mmc_plat mmc_plat = {
373 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
377 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
378 .host_caps = MMC_MODE_4BIT,
379 .b_max = DAVINCI_MAX_BLOCKS,
383 U_BOOT_DRVINFO(omapl138_mmc) = {
384 .name = "ti_da830_mmc",
388 void spl_board_init(void)
390 davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins));