1 // SPDX-License-Identifier: GPL-2.0+
5 * Generated code from MX8M_DDR_tool
6 * Align with uboot version:
7 * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
10 #include <linux/kernel.h>
11 #include <asm/arch/ddr.h>
13 static struct dram_cfg_param ddr_ddrc_cfg[] = {
14 /** Initialize DDRC registers **/
17 { 0x3d400000, 0xa1080020 },
18 { 0x3d400020, 0x203 },
19 { 0x3d400024, 0x3a980 },
20 { 0x3d400064, 0x5b00d2 },
21 { 0x3d4000d0, 0xc00305ba },
22 { 0x3d4000d4, 0x940000 },
23 { 0x3d4000dc, 0xd4002d },
24 { 0x3d4000e0, 0x310000 },
25 { 0x3d4000e8, 0x66004d },
26 { 0x3d4000ec, 0x16004d },
27 { 0x3d400100, 0x191e1920 },
28 { 0x3d400104, 0x60630 },
29 { 0x3d40010c, 0xb0b000 },
30 { 0x3d400110, 0xe04080e },
31 { 0x3d400114, 0x2040c0c },
32 { 0x3d400118, 0x1010007 },
33 { 0x3d40011c, 0x401 },
34 { 0x3d400130, 0x20600 },
35 { 0x3d400134, 0xc100002 },
37 { 0x3d400144, 0x96004b },
38 { 0x3d400180, 0x2ee0017 },
39 { 0x3d400184, 0x2605b8e },
41 { 0x3d400190, 0x497820a },
42 { 0x3d400194, 0x80303 },
43 { 0x3d4001b4, 0x170a },
44 { 0x3d4001a0, 0xe0400018 },
45 { 0x3d4001a4, 0xdf00e4 },
46 { 0x3d4001a8, 0x80000000 },
50 { 0x3d4000f4, 0xc99 },
51 { 0x3d400108, 0x70e1617 },
54 { 0x3d400210, 0x1f1f },
55 { 0x3d400204, 0x80808 },
56 { 0x3d400214, 0x7070707 },
57 { 0x3d400218, 0x7070707 },
58 { 0x3d400250, 0x29001701 },
60 { 0x3d40025c, 0x4000030 },
61 { 0x3d400264, 0x900093e7 },
62 { 0x3d40026c, 0x2005574 },
63 { 0x3d400400, 0x111 },
64 { 0x3d400408, 0x72ff },
65 { 0x3d400494, 0x2100e07 },
66 { 0x3d400498, 0x620096 },
67 { 0x3d40049c, 0x1100e07 },
68 { 0x3d4004a0, 0xc8012c },
70 { 0x3d402024, 0x7d00 },
71 { 0x3d402050, 0x20d040 },
72 { 0x3d402064, 0xc001c },
73 { 0x3d4020dc, 0x840000 },
74 { 0x3d4020e0, 0x310000 },
75 { 0x3d4020e8, 0x66004d },
76 { 0x3d4020ec, 0x16004d },
77 { 0x3d402100, 0xa040305 },
78 { 0x3d402104, 0x30407 },
79 { 0x3d402108, 0x203060b },
80 { 0x3d40210c, 0x505000 },
81 { 0x3d402110, 0x2040202 },
82 { 0x3d402114, 0x2030202 },
83 { 0x3d402118, 0x1010004 },
84 { 0x3d40211c, 0x301 },
85 { 0x3d402130, 0x20300 },
86 { 0x3d402134, 0xa100002 },
88 { 0x3d402144, 0x14000a },
89 { 0x3d402180, 0x640004 },
90 { 0x3d402190, 0x3818200 },
91 { 0x3d402194, 0x80303 },
92 { 0x3d4021b4, 0x100 },
93 { 0x3d4020f4, 0xc99 },
95 { 0x3d403024, 0x1f40 },
96 { 0x3d403050, 0x20d040 },
97 { 0x3d403064, 0x30007 },
98 { 0x3d4030dc, 0x840000 },
99 { 0x3d4030e0, 0x310000 },
100 { 0x3d4030e8, 0x66004d },
101 { 0x3d4030ec, 0x16004d },
102 { 0x3d403100, 0xa010102 },
103 { 0x3d403104, 0x30404 },
104 { 0x3d403108, 0x203060b },
105 { 0x3d40310c, 0x505000 },
106 { 0x3d403110, 0x2040202 },
107 { 0x3d403114, 0x2030202 },
108 { 0x3d403118, 0x1010004 },
109 { 0x3d40311c, 0x301 },
110 { 0x3d403130, 0x20300 },
111 { 0x3d403134, 0xa100002 },
113 { 0x3d403144, 0x50003 },
114 { 0x3d403180, 0x190004 },
115 { 0x3d403190, 0x3818200 },
116 { 0x3d403194, 0x80303 },
117 { 0x3d4031b4, 0x100 },
118 { 0x3d4030f4, 0xc99 },
122 /* PHY Initialize Configuration */
123 static struct dram_cfg_param ddr_ddrphy_cfg[] = {
326 /* ddr phy trained csr */
327 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
1049 /* P0 message block paremeter for training firmware */
1050 static struct dram_cfg_param ddr_fsp0_cfg[] = {
1054 { 0x54005, 0x2228 },
1056 { 0x54008, 0x131f },
1060 { 0x54019, 0x2dd4 },
1062 { 0x5401b, 0x4d66 },
1063 { 0x5401c, 0x4d00 },
1065 { 0x5401f, 0x2dd4 },
1067 { 0x54021, 0x4d66 },
1068 { 0x54022, 0x4d00 },
1070 { 0x5402b, 0x1000 },
1072 { 0x54032, 0xd400 },
1073 { 0x54033, 0x312d },
1074 { 0x54034, 0x6600 },
1077 { 0x54037, 0x1600 },
1078 { 0x54038, 0xd400 },
1079 { 0x54039, 0x312d },
1080 { 0x5403a, 0x6600 },
1083 { 0x5403d, 0x1600 },
1087 /* P1 message block paremeter for training firmware */
1088 static struct dram_cfg_param ddr_fsp1_cfg[] = {
1093 { 0x54005, 0x2228 },
1095 { 0x54008, 0x121f },
1101 { 0x5401b, 0x4d66 },
1102 { 0x5401c, 0x4d00 },
1106 { 0x54021, 0x4d66 },
1107 { 0x54022, 0x4d00 },
1109 { 0x5402b, 0x1000 },
1111 { 0x54032, 0x8400 },
1112 { 0x54033, 0x3100 },
1113 { 0x54034, 0x6600 },
1116 { 0x54037, 0x1600 },
1117 { 0x54038, 0x8400 },
1118 { 0x54039, 0x3100 },
1119 { 0x5403a, 0x6600 },
1122 { 0x5403d, 0x1600 },
1126 /* P2 message block paremeter for training firmware */
1127 static struct dram_cfg_param ddr_fsp2_cfg[] = {
1132 { 0x54005, 0x2228 },
1134 { 0x54008, 0x121f },
1140 { 0x5401b, 0x4d66 },
1141 { 0x5401c, 0x4d00 },
1145 { 0x54021, 0x4d66 },
1146 { 0x54022, 0x4d00 },
1148 { 0x5402b, 0x1000 },
1150 { 0x54032, 0x8400 },
1151 { 0x54033, 0x3100 },
1152 { 0x54034, 0x6600 },
1155 { 0x54037, 0x1600 },
1156 { 0x54038, 0x8400 },
1157 { 0x54039, 0x3100 },
1158 { 0x5403a, 0x6600 },
1161 { 0x5403d, 0x1600 },
1165 /* P0 2D message block paremeter for training firmware */
1166 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1170 { 0x54005, 0x2228 },
1176 { 0x54010, 0x1f7f },
1178 { 0x54019, 0x2dd4 },
1180 { 0x5401b, 0x4d66 },
1181 { 0x5401c, 0x4d00 },
1183 { 0x5401f, 0x2dd4 },
1185 { 0x54021, 0x4d66 },
1186 { 0x54022, 0x4d00 },
1188 { 0x5402b, 0x1000 },
1190 { 0x54032, 0xd400 },
1191 { 0x54033, 0x312d },
1192 { 0x54034, 0x6600 },
1195 { 0x54037, 0x1600 },
1196 { 0x54038, 0xd400 },
1197 { 0x54039, 0x312d },
1198 { 0x5403a, 0x6600 },
1201 { 0x5403d, 0x1600 },
1205 /* DRAM PHY init engine image */
1206 static struct dram_cfg_param ddr_phy_pie[] = {
1265 { 0x9005c, 0x40c0 },
1271 { 0x90062, 0x4040 },
1344 { 0x40001, 0x4008 },
1348 { 0x40002, 0x4040 },
1358 { 0x40044, 0x1740 },
1366 { 0x40046, 0x2001 },
1370 { 0x40047, 0x2800 },
1378 { 0x40049, 0x1400 },
1388 { 0x4000c, 0x4028 },
1400 { 0x4000f, 0x4040 },
1404 { 0x40010, 0x2604 },
1411 { 0x40071, 0x2002 },
1416 { 0x40013, 0x2604 },
1423 { 0x40074, 0x2002 },
1424 { 0x40015, 0x4040 },
1430 { 0x40056, 0x1200 },
1434 { 0x40057, 0x1300 },
1438 { 0x40058, 0x1200 },
1442 { 0x40059, 0x1300 },
1444 { 0x4001a, 0x4808 },
1482 { 0x900c9, 0x8568 },
1491 { 0x900d2, 0x8558 },
1496 { 0x900d7, 0x1ff8 },
1497 { 0x900d8, 0x85a8 },
1506 { 0x900e1, 0x8310 },
1509 { 0x900e4, 0xa310 },
1521 { 0x900f0, 0x8310 },
1524 { 0x900f3, 0xa310 },
1526 { 0x900f5, 0x1ff8 },
1527 { 0x900f6, 0x85a8 },
1539 { 0x90102, 0x8b10 },
1542 { 0x90105, 0xab10 },
1554 { 0x90111, 0x8b10 },
1557 { 0x90114, 0xab10 },
1572 { 0x90123, 0x8080 },
1587 { 0x90132, 0x8080 },
1593 { 0x90138, 0x8568 },
1602 { 0x90141, 0x8558 },
1614 { 0x9014d, 0x8558 },
1632 { 0x9015f, 0x8140 },
1635 { 0x90162, 0x8138 },
1665 { 0x90180, 0x8140 },
1710 { 0x9000f, 0x6110 },
1711 { 0x90010, 0x2152 },
1712 { 0x90011, 0xdfbd },
1714 { 0x90013, 0x6152 },
1744 { 0x10002, 0x6209 },
1758 { 0x11002, 0x6209 },
1772 { 0x12002, 0x6209 },
1786 { 0x13002, 0x6209 },
1801 static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
1805 .fw_type = FW_1D_IMAGE,
1806 .fsp_cfg = ddr_fsp0_cfg,
1807 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
1812 .fw_type = FW_1D_IMAGE,
1813 .fsp_cfg = ddr_fsp1_cfg,
1814 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
1819 .fw_type = FW_1D_IMAGE,
1820 .fsp_cfg = ddr_fsp2_cfg,
1821 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
1826 .fw_type = FW_2D_IMAGE,
1827 .fsp_cfg = ddr_fsp0_2d_cfg,
1828 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
1832 /* ddr timing config params */
1833 struct dram_timing_info dmo_imx8mm_sbc_dram_timing_16_32 = {
1834 .ddrc_cfg = ddr_ddrc_cfg,
1835 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
1836 .ddrphy_cfg = ddr_ddrphy_cfg,
1837 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
1838 .fsp_msg = ddr_dram_fsp_msg,
1839 .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
1840 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1841 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
1842 .ddrphy_pie = ddr_phy_pie,
1843 .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
1844 .fsp_table = { 3000, 400, 100, },