1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2023 CS GROUP France
4 * Florent TRINH THAI (florent.trinh-thai@csgroup.eu)
5 * Stephane FRANJOU (stephane.franjou@csgroup.eu)
10 #include <linux/bitops.h>
11 #include <linux/mtd/rawnand.h>
14 #define BIT_CLE BIT(6)
15 #define BIT_ALE BIT(5)
17 static u32 nand_mask(unsigned int ctrl)
19 return ((ctrl & NAND_CLE) ? BIT_CLE : 0) |
20 ((ctrl & NAND_ALE) ? BIT_ALE : 0);
23 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
25 immap_t __iomem *immr = (immap_t *)CONFIG_SYS_IMMR;
26 struct nand_chip *chip = mtd_to_nand(mtdinfo);
28 if (ctrl & NAND_CTRL_CHANGE)
29 clrsetbits_be32(&immr->qepio.ioport[2].pdat,
30 BIT_CLE | BIT_ALE, nand_mask(ctrl));
32 if (cmd != NAND_CMD_NONE)
33 out_8(chip->IO_ADDR_W, cmd);
36 int board_nand_init(struct nand_chip *nand)
38 nand->chip_delay = 60;
39 nand->ecc.mode = NAND_ECC_SOFT;
40 nand->cmd_ctrl = nand_hwcontrol;