board/congatec/cgtqmx6eval/cgtqmx6eval.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  * Based on mx6qsabrelite.c file
   4  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
   5  * Leo Sartre, <lsartre@adeneo-embedded.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/iomux-v3.h>
  18 #include <asm/imx-common/boot_mode.h>
  19 #include <asm/imx-common/mxc_i2c.h>
  20 #include <mmc.h>
  21 #include <fsl_esdhc.h>
  22 #include <i2c.h>
  23 #include <power/pmic.h>
  24 #include <power/pfuze100_pmic.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
  29         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  30
  31 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
  32         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  33
  34 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  35         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  36         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  37         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  38
  39 #define MX6Q_QMX6_PFUZE_MUX             IMX_GPIO_NR(6, 9)
  40
  41 int dram_init(void)
  42 {
  43         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  44
  45         return 0;
  46 }
  47
  48 static iomux_v3_cfg_t const uart2_pads[] = {
  49         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  50         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  51 };
  52
  53 static iomux_v3_cfg_t const usdhc2_pads[] = {
  54         MX6_PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  55         MX6_PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  56         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  57         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  58         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  59         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  60         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  61 };
  62
  63 static iomux_v3_cfg_t const usdhc3_pads[] = {
  64         MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  65         MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  66         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  67         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  68         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  69         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75 };
  76
  77 static iomux_v3_cfg_t const usdhc4_pads[] = {
  78         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  89 };
  90
  91 static iomux_v3_cfg_t const usb_otg_pads[] = {
  92         MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  93         MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
  94 };
  95
  96 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  97 struct i2c_pads_info i2c_pad_info1 = {
  98         .scl = {
  99                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 100                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 101                 .gp = IMX_GPIO_NR(4, 12)
 102         },
 103         .sda = {
 104                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 105                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 106                 .gp = IMX_GPIO_NR(4, 13)
 107         }
 108 };
 109
 110 #define I2C_PMIC        1       /* I2C2 port is used to connect to the PMIC */
 111
 112 struct interface_level {
 113         char *name;
 114         uchar value;
 115 };
 116
 117 static struct interface_level mipi_levels[] = {
 118         {"0V0", 0x00},
 119         {"2V5", 0x17},
 120 };
 121
 122 /* setup board specific PMIC */
 123 int power_init_board(void)
 124 {
 125         struct pmic *p;
 126         u32 id1, id2, i;
 127         int ret;
 128         char const *lv_mipi;
 129
 130         /* configure I2C multiplexer */
 131         gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1);
 132
 133         power_pfuze100_init(I2C_PMIC);
 134         p = pmic_get("PFUZE100");
 135         if (!p)
 136                 return -EINVAL;
 137
 138         ret = pmic_probe(p);
 139         if (ret)
 140                 return ret;
 141
 142         pmic_reg_read(p, PFUZE100_DEVICEID, &id1);
 143         pmic_reg_read(p, PFUZE100_REVID, &id2);
 144         printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2);
 145
 146         if (id2 >= 0x20)
 147                 return 0;
 148
 149         /* set level of MIPI if specified */
 150         lv_mipi = getenv("lv_mipi");
 151         if (lv_mipi)
 152                 return 0;
 153
 154         for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
 155                 if (!strcmp(mipi_levels[i].name, lv_mipi)) {
 156                         printf("set MIPI level %s\n",
 157                                mipi_levels[i].name);
 158                         ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
 159                                              mipi_levels[i].value);
 160                         if (ret)
 161                                 return ret;
 162                 }
 163         }
 164
 165         return 0;
 166 }
 167
 168 static void setup_iomux_uart(void)
 169 {
 170         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 171 }
 172
 173 #ifdef CONFIG_FSL_ESDHC
 174 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 175         {USDHC2_BASE_ADDR},
 176         {USDHC3_BASE_ADDR},
 177         {USDHC4_BASE_ADDR},
 178 };
 179
 180 int board_mmc_getcd(struct mmc *mmc)
 181 {
 182         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 183         int ret = 0;
 184
 185         switch (cfg->esdhc_base) {
 186         case USDHC2_BASE_ADDR:
 187                 gpio_direction_input(IMX_GPIO_NR(1, 4));
 188                 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
 189                 break;
 190         case USDHC3_BASE_ADDR:
 191                 ret = 1;        /* eMMC is always present */
 192                 break;
 193         case USDHC4_BASE_ADDR:
 194                 gpio_direction_input(IMX_GPIO_NR(2, 6));
 195                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 196                 break;
 197         default:
 198                 printf("Bad USDHC interface\n");
 199         }
 200
 201         return ret;
 202 }
 203
 204 int board_mmc_init(bd_t *bis)
 205 {
 206         s32 status = 0;
 207         int i;
 208
 209         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 210         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 211         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 212
 213         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 214         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 215         imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 216
 217         for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) {
 218                 status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 219                 if (status)
 220                         return status;
 221         }
 222
 223         return 0;
 224 }
 225 #endif
 226
 227 int board_ehci_hcd_init(int port)
 228 {
 229         switch (port) {
 230         case 0:
 231                 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 232                                                  ARRAY_SIZE(usb_otg_pads));
 233                 /*
 234                  * set daisy chain for otg_pin_id on 6q.
 235                  * for 6dl, this bit is reserved
 236                  */
 237                 imx_iomux_set_gpr_register(1, 13, 1, 1);
 238                 break;
 239         case 1:
 240                 /* nothing to do */
 241                 break;
 242         default:
 243                 printf("Invalid USB port: %d\n", port);
 244                 return -EINVAL;
 245         }
 246
 247         return 0;
 248 }
 249
 250 int board_ehci_power(int port, int on)
 251 {
 252         switch (port) {
 253         case 0:
 254                 break;
 255         case 1:
 256                 gpio_direction_output(IMX_GPIO_NR(5, 5), on);
 257                 break;
 258         default:
 259                 printf("Invalid USB port: %d\n", port);
 260                 return -EINVAL;
 261         }
 262
 263         return 0;
 264 }
 265
 266 int board_early_init_f(void)
 267 {
 268         setup_iomux_uart();
 269
 270         return 0;
 271 }
 272
 273 int board_init(void)
 274 {
 275         /* address of boot parameters */
 276         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 277
 278         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 279
 280         return 0;
 281 }
 282
 283 int checkboard(void)
 284 {
 285         puts("Board: Conga-QEVAL QMX6 Quad\n");
 286
 287         return 0;
 288 }
 289
 290 #ifdef CONFIG_CMD_BMODE
 291 static const struct boot_mode board_boot_modes[] = {
 292         /* 4 bit bus width */
 293         {"mmc0",        MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
 294         {"mmc1",        MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
 295         {NULL,          0},
 296 };
 297 #endif
 298
 299 int misc_init_r(void)
 300 {
 301 #ifdef CONFIG_CMD_BMODE
 302         add_board_boot_modes(board_boot_modes);
 303 #endif
 304         return 0;
 305 }