board/congatec/cgtqmx6eval/cgtqmx6eval.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  * Based on mx6qsabrelite.c file
   4  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
   5  * Leo Sartre, <lsartre@adeneo-embedded.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/iomux-v3.h>
  18 #include <asm/imx-common/boot_mode.h>
  19 #include <asm/imx-common/mxc_i2c.h>
  20 #include <mmc.h>
  21 #include <fsl_esdhc.h>
  22 #include <i2c.h>
  23 #include <power/pmic.h>
  24 #include <power/pfuze100_pmic.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
  29         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  30
  31 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
  32         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  33
  34 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  35         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  36         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  37         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  38
  39 #define MX6Q_QMX6_PFUZE_MUX             IMX_GPIO_NR(6, 9)
  40
  41 int dram_init(void)
  42 {
  43         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  44
  45         return 0;
  46 }
  47
  48 static iomux_v3_cfg_t const uart2_pads[] = {
  49         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  50         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  51 };
  52
  53 static iomux_v3_cfg_t const usdhc2_pads[] = {
  54         MX6_PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  55         MX6_PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  56         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  57         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  58         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  59         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  60         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  61 };
  62
  63 static iomux_v3_cfg_t const usdhc3_pads[] = {
  64         MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  65         MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  66         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  67         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  68         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  69         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75 };
  76
  77 static iomux_v3_cfg_t const usdhc4_pads[] = {
  78         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  89 };
  90
  91 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  92 struct i2c_pads_info i2c_pad_info1 = {
  93         .scl = {
  94                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
  95                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
  96                 .gp = IMX_GPIO_NR(4, 12)
  97         },
  98         .sda = {
  99                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 100                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 101                 .gp = IMX_GPIO_NR(4, 13)
 102         }
 103 };
 104
 105 #define I2C_PMIC        1       /* I2C2 port is used to connect to the PMIC */
 106
 107 struct interface_level {
 108         char *name;
 109         uchar value;
 110 };
 111
 112 static struct interface_level mipi_levels[] = {
 113         {"0V0", 0x00},
 114         {"2V5", 0x17},
 115 };
 116
 117 /* setup board specific PMIC */
 118 int power_init_board(void)
 119 {
 120         struct pmic *p;
 121         u32 id1, id2, i;
 122         int ret;
 123         char const *lv_mipi;
 124
 125         /* configure I2C multiplexer */
 126         gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1);
 127
 128         power_pfuze100_init(I2C_PMIC);
 129         p = pmic_get("PFUZE100");
 130         if (!p)
 131                 return -EINVAL;
 132
 133         ret = pmic_probe(p);
 134         if (ret)
 135                 return ret;
 136
 137         pmic_reg_read(p, PFUZE100_DEVICEID, &id1);
 138         pmic_reg_read(p, PFUZE100_REVID, &id2);
 139         printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2);
 140
 141         if (id2 >= 0x20)
 142                 return 0;
 143
 144         /* set level of MIPI if specified */
 145         lv_mipi = getenv("lv_mipi");
 146         if (lv_mipi)
 147                 return 0;
 148
 149         for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
 150                 if (!strcmp(mipi_levels[i].name, lv_mipi)) {
 151                         printf("set MIPI level %s\n",
 152                                mipi_levels[i].name);
 153                         ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
 154                                              mipi_levels[i].value);
 155                         if (ret)
 156                                 return ret;
 157                 }
 158         }
 159
 160         return 0;
 161 }
 162
 163 static void setup_iomux_uart(void)
 164 {
 165         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 166 }
 167
 168 #ifdef CONFIG_FSL_ESDHC
 169 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 170         {USDHC2_BASE_ADDR},
 171         {USDHC3_BASE_ADDR},
 172         {USDHC4_BASE_ADDR},
 173 };
 174
 175 int board_mmc_getcd(struct mmc *mmc)
 176 {
 177         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 178         int ret = 0;
 179
 180         switch (cfg->esdhc_base) {
 181         case USDHC2_BASE_ADDR:
 182                 gpio_direction_input(IMX_GPIO_NR(1, 4));
 183                 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
 184                 break;
 185         case USDHC3_BASE_ADDR:
 186                 ret = 1;        /* eMMC is always present */
 187                 break;
 188         case USDHC4_BASE_ADDR:
 189                 gpio_direction_input(IMX_GPIO_NR(2, 6));
 190                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 191                 break;
 192         default:
 193                 printf("Bad USDHC interface\n");
 194         }
 195
 196         return ret;
 197 }
 198
 199 int board_mmc_init(bd_t *bis)
 200 {
 201         s32 status = 0;
 202         int i;
 203
 204         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 205         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 206         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 207
 208         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 209         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 210         imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 211
 212         for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) {
 213                 status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 214                 if (status)
 215                         return status;
 216         }
 217
 218         return 0;
 219 }
 220 #endif
 221
 222 int board_early_init_f(void)
 223 {
 224         setup_iomux_uart();
 225
 226         return 0;
 227 }
 228
 229 int board_init(void)
 230 {
 231         /* address of boot parameters */
 232         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 233
 234         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 235
 236         return 0;
 237 }
 238
 239 int checkboard(void)
 240 {
 241         puts("Board: Conga-QEVAL QMX6 Quad\n");
 242
 243         return 0;
 244 }
 245
 246 #ifdef CONFIG_CMD_BMODE
 247 static const struct boot_mode board_boot_modes[] = {
 248         /* 4 bit bus width */
 249         {"mmc0",        MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
 250         {"mmc1",        MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
 251         {NULL,          0},
 252 };
 253 #endif
 254
 255 int misc_init_r(void)
 256 {
 257 #ifdef CONFIG_CMD_BMODE
 258         add_board_boot_modes(board_boot_modes);
 259 #endif
 260         return 0;
 261 }