board/compulab/cm_fx6/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * SPL specific code for Compulab CM-FX6 board
   4  *
   5  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
   6  *
   7  * Author: Nikita Kiryanov <nikita@compulab.co.il>
   8  */
   9
  10 #include <common.h>
  11 #include <clock_legacy.h>
  12 #include <init.h>
  13 #include <spl.h>
  14 #include <asm/io.h>
  15 #include <asm/gpio.h>
  16 #include <asm/arch/mx6-ddr.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/crm_regs.h>
  20 #include <asm/mach-imx/iomux-v3.h>
  21 #include <fsl_esdhc_imx.h>
  22 #include "common.h"
  23
  24 enum ddr_config {
  25         DDR_16BIT_256MB,
  26         DDR_32BIT_512MB,
  27         DDR_32BIT_1GB,
  28         DDR_64BIT_1GB,
  29         DDR_64BIT_2GB,
  30         DDR_64BIT_4GB,
  31         DDR_UNKNOWN,
  32 };
  33
  34 /*
  35  * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to
  36  * Freescale QRM, but this is exactly the value used by the automatic
  37  * calibration script and it works also in all our tests, so we leave
  38  * it as is at this point.
  39  */
  40 #define CM_FX6_DDR_IOMUX_CFG \
  41         .dram_sdqs0     = 0x00000038, \
  42         .dram_sdqs1     = 0x00000038, \
  43         .dram_sdqs2     = 0x00000038, \
  44         .dram_sdqs3     = 0x00000038, \
  45         .dram_sdqs4     = 0x00000038, \
  46         .dram_sdqs5     = 0x00000038, \
  47         .dram_sdqs6     = 0x00000038, \
  48         .dram_sdqs7     = 0x00000038, \
  49         .dram_dqm0      = 0x00000038, \
  50         .dram_dqm1      = 0x00000038, \
  51         .dram_dqm2      = 0x00000038, \
  52         .dram_dqm3      = 0x00000038, \
  53         .dram_dqm4      = 0x00000038, \
  54         .dram_dqm5      = 0x00000038, \
  55         .dram_dqm6      = 0x00000038, \
  56         .dram_dqm7      = 0x00000038, \
  57         .dram_cas       = 0x00000038, \
  58         .dram_ras       = 0x00000038, \
  59         .dram_sdclk_0   = 0x00000038, \
  60         .dram_sdclk_1   = 0x00000038, \
  61         .dram_sdcke0    = 0x00003000, \
  62         .dram_sdcke1    = 0x00003000, \
  63         .dram_reset     = 0x00000038, \
  64         .dram_sdba2     = 0x00000000, \
  65         .dram_sdodt0    = 0x00000038, \
  66         .dram_sdodt1    = 0x00000038,
  67
  68 #define CM_FX6_GPR_IOMUX_CFG \
  69         .grp_b0ds       = 0x00000038, \
  70         .grp_b1ds       = 0x00000038, \
  71         .grp_b2ds       = 0x00000038, \
  72         .grp_b3ds       = 0x00000038, \
  73         .grp_b4ds       = 0x00000038, \
  74         .grp_b5ds       = 0x00000038, \
  75         .grp_b6ds       = 0x00000038, \
  76         .grp_b7ds       = 0x00000038, \
  77         .grp_addds      = 0x00000038, \
  78         .grp_ddrmode_ctl = 0x00020000, \
  79         .grp_ddrpke     = 0x00000000, \
  80         .grp_ddrmode    = 0x00020000, \
  81         .grp_ctlds      = 0x00000038, \
  82         .grp_ddr_type   = 0x000C0000,
  83
  84 static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG };
  85 static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG };
  86 static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG };
  87 static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG };
  88
  89 static struct mx6_mmdc_calibration cm_fx6_calib_s = {
  90         .p0_mpwldectrl0 = 0x005B0061,
  91         .p0_mpwldectrl1 = 0x004F0055,
  92         .p0_mpdgctrl0   = 0x0314030C,
  93         .p0_mpdgctrl1   = 0x025C0268,
  94         .p0_mprddlctl   = 0x42464646,
  95         .p0_mpwrdlctl   = 0x36322C34,
  96 };
  97
  98 static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
  99         .cs1_mirror     = 1,
 100         .cs_density     = 16,
 101         .bi_on          = 1,
 102         .rtt_nom        = 1,
 103         .rtt_wr         = 0,
 104         .ralat          = 5,
 105         .walat          = 1,
 106         .mif3_mode      = 3,
 107         .rst_to_cke     = 0x23,
 108         .sde_to_rst     = 0x10,
 109 };
 110
 111 static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {
 112         .mem_speed      = 800,
 113         .density        = 4,
 114         .rowaddr        = 14,
 115         .coladdr        = 10,
 116         .pagesz         = 2,
 117         .trcd           = 1800,
 118         .trcmin         = 5200,
 119         .trasmin        = 3600,
 120         .SRT            = 0,
 121 };
 122
 123 static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset)
 124 {
 125         if (reset)
 126                 ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
 127
 128         switch (dram_config) {
 129         case DDR_16BIT_256MB:
 130                 cm_fx6_sysinfo_s.dsize = 0;
 131                 cm_fx6_sysinfo_s.ncs = 1;
 132                 break;
 133         case DDR_32BIT_512MB:
 134                 cm_fx6_sysinfo_s.dsize = 1;
 135                 cm_fx6_sysinfo_s.ncs = 1;
 136                 break;
 137         case DDR_32BIT_1GB:
 138                 cm_fx6_sysinfo_s.dsize = 1;
 139                 cm_fx6_sysinfo_s.ncs = 2;
 140                 break;
 141         default:
 142                 puts("Tried to setup invalid DDR configuration\n");
 143                 hang();
 144         }
 145
 146         mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s);
 147         udelay(100);
 148 }
 149
 150 static struct mx6_mmdc_calibration cm_fx6_calib_q = {
 151         .p0_mpwldectrl0 = 0x00630068,
 152         .p0_mpwldectrl1 = 0x0068005D,
 153         .p0_mpdgctrl0   = 0x04140428,
 154         .p0_mpdgctrl1   = 0x037C037C,
 155         .p0_mprddlctl   = 0x3C30303A,
 156         .p0_mpwrdlctl   = 0x3A344038,
 157         .p1_mpwldectrl0 = 0x0035004C,
 158         .p1_mpwldectrl1 = 0x00170026,
 159         .p1_mpdgctrl0   = 0x0374037C,
 160         .p1_mpdgctrl1   = 0x0350032C,
 161         .p1_mprddlctl   = 0x30322A3C,
 162         .p1_mpwrdlctl   = 0x48304A3E,
 163 };
 164
 165 static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
 166         .cs_density     = 16,
 167         .cs1_mirror     = 1,
 168         .bi_on          = 1,
 169         .rtt_nom        = 1,
 170         .rtt_wr         = 0,
 171         .ralat          = 5,
 172         .walat          = 1,
 173         .mif3_mode      = 3,
 174         .rst_to_cke     = 0x23,
 175         .sde_to_rst     = 0x10,
 176         .refsel = 1,            /* Refresh cycles at 32KHz */
 177         .refr = 7,              /* 8 refresh commands per refresh cycle */
 178 };
 179
 180 static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {
 181         .mem_speed      = 1066,
 182         .density        = 4,
 183         .rowaddr        = 14,
 184         .coladdr        = 10,
 185         .pagesz         = 2,
 186         .trcd           = 1324,
 187         .trcmin         = 59500,
 188         .trasmin        = 9750,
 189         .SRT            = 0,
 190 };
 191
 192 static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset)
 193 {
 194         if (reset)
 195                 ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
 196
 197         cm_fx6_ddr3_cfg_q.rowaddr = 14;
 198         switch (dram_config) {
 199         case DDR_16BIT_256MB:
 200                 cm_fx6_sysinfo_q.dsize = 0;
 201                 cm_fx6_sysinfo_q.ncs = 1;
 202                 break;
 203         case DDR_32BIT_512MB:
 204                 cm_fx6_sysinfo_q.dsize = 1;
 205                 cm_fx6_sysinfo_q.ncs = 1;
 206                 break;
 207         case DDR_64BIT_1GB:
 208                 cm_fx6_sysinfo_q.dsize = 2;
 209                 cm_fx6_sysinfo_q.ncs = 1;
 210                 break;
 211         case DDR_64BIT_2GB:
 212                 cm_fx6_sysinfo_q.dsize = 2;
 213                 cm_fx6_sysinfo_q.ncs = 2;
 214                 break;
 215         case DDR_64BIT_4GB:
 216                 cm_fx6_sysinfo_q.dsize = 2;
 217                 cm_fx6_sysinfo_q.ncs = 2;
 218                 cm_fx6_ddr3_cfg_q.rowaddr = 15;
 219                 break;
 220         default:
 221                 puts("Tried to setup invalid DDR configuration\n");
 222                 hang();
 223         }
 224
 225         mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q);
 226         udelay(100);
 227 }
 228
 229 static int cm_fx6_spl_dram_init(void)
 230 {
 231         unsigned long bank1_size, bank2_size;
 232
 233         switch (get_cpu_type()) {
 234         case MXC_CPU_MX6SOLO:
 235                 mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s);
 236
 237                 spl_mx6s_dram_init(DDR_32BIT_1GB, false);
 238                 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
 239                 bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 0x80000000);
 240                 if (bank1_size == 0x20000000) {
 241                         if (bank2_size == 0x20000000)
 242                                 return 0;
 243
 244                         spl_mx6s_dram_init(DDR_32BIT_512MB, true);
 245                         return 0;
 246                 }
 247
 248                 spl_mx6s_dram_init(DDR_16BIT_256MB, true);
 249                 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
 250                 if (bank1_size == 0x10000000)
 251                         return 0;
 252
 253                 break;
 254         case MXC_CPU_MX6D:
 255         case MXC_CPU_MX6Q:
 256                 mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q);
 257
 258                 spl_mx6q_dram_init(DDR_64BIT_4GB, false);
 259                 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
 260                 if (bank1_size == 0x80000000)
 261                         return 0;
 262
 263                 if (bank1_size == 0x40000000) {
 264                         bank2_size = get_ram_size((long int *)PHYS_SDRAM_2,
 265                                                                 0x80000000);
 266                         if (bank2_size == 0x40000000) {
 267                                 /* Don't do a full reset here */
 268                                 spl_mx6q_dram_init(DDR_64BIT_2GB, false);
 269                         } else {
 270                                 spl_mx6q_dram_init(DDR_64BIT_1GB, true);
 271                         }
 272
 273                         return 0;
 274                 }
 275
 276                 spl_mx6q_dram_init(DDR_32BIT_512MB, true);
 277                 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
 278                 if (bank1_size == 0x20000000)
 279                         return 0;
 280
 281                 spl_mx6q_dram_init(DDR_16BIT_256MB, true);
 282                 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
 283                 if (bank1_size == 0x10000000)
 284                         return 0;
 285
 286                 break;
 287         }
 288
 289         return -1;
 290 }
 291
 292 static iomux_v3_cfg_t const uart4_pads[] = {
 293         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 294         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 295 };
 296
 297 static void cm_fx6_setup_uart(void)
 298 {
 299         SETUP_IOMUX_PADS(uart4_pads);
 300         enable_uart_clk(1);
 301 }
 302
 303 #ifdef CONFIG_SPL_SPI_SUPPORT
 304 static void cm_fx6_setup_ecspi(void)
 305 {
 306         cm_fx6_set_ecspi_iomux();
 307         enable_spi_clk(1, 0);
 308 }
 309 #else
 310 static void cm_fx6_setup_ecspi(void) { }
 311 #endif
 312
 313 void board_init_f(ulong dummy)
 314 {
 315         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 316
 317         /*
 318          * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
 319          * initializes DMA very early (before all board code), so the only
 320          * opportunity we have to initialize APBHDMA clocks is in SPL.
 321          */
 322         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 323         enable_usdhc_clk(1, 2);
 324
 325         arch_cpu_init();
 326         timer_init();
 327         cm_fx6_setup_ecspi();
 328         cm_fx6_setup_uart();
 329         get_clocks();
 330         preloader_console_init();
 331         gpio_direction_output(CM_FX6_GREEN_LED, 1);
 332         if (cm_fx6_spl_dram_init()) {
 333                 puts("!!!ERROR!!! DRAM detection failed!!!\n");
 334                 hang();
 335         }
 336 }
 337
 338 void board_boot_order(u32 *spl_boot_list)
 339 {
 340         spl_boot_list[0] = spl_boot_device();
 341         switch (spl_boot_list[0]) {
 342         case BOOT_DEVICE_SPI:
 343                 spl_boot_list[1] = BOOT_DEVICE_MMC1;
 344                 break;
 345         case BOOT_DEVICE_MMC1:
 346                 spl_boot_list[1] = BOOT_DEVICE_SPI;
 347                 break;
 348         }
 349 }
 350
 351 #ifdef CONFIG_SPL_MMC_SUPPORT
 352 static struct fsl_esdhc_cfg usdhc_cfg = {
 353         .esdhc_base = USDHC3_BASE_ADDR,
 354         .max_bus_width = 4,
 355 };
 356
 357 int board_mmc_init(bd_t *bis)
 358 {
 359         cm_fx6_set_usdhc_iomux();
 360
 361         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 362
 363         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 364 }
 365 #endif