board/compulab/cm_fx6/cm_fx6.c

   1 /*
   2  * Board functions for Compulab CM-FX6 board
   3  *
   4  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
   5  *
   6  * Author: Nikita Kiryanov <nikita@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <fsl_esdhc.h>
  13 #include <miiphy.h>
  14 #include <netdev.h>
  15 #include <fdt_support.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/arch/iomux.h>
  19 #include <asm/imx-common/mxc_i2c.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include "common.h"
  23 #include "../common/eeprom.h"
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #ifdef CONFIG_SYS_I2C_MXC
  28 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  29                         PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  30                         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  31
  32 I2C_PADS(i2c0_pads,
  33          PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  34          PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  35          IMX_GPIO_NR(3, 21),
  36          PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  37          PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  38          IMX_GPIO_NR(3, 28));
  39
  40 I2C_PADS(i2c1_pads,
  41          PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  42          PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  43          IMX_GPIO_NR(4, 12),
  44          PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  45          PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  46          IMX_GPIO_NR(4, 13));
  47
  48 I2C_PADS(i2c2_pads,
  49          PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
  50          PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  51          IMX_GPIO_NR(1, 3),
  52          PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
  53          PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
  54          IMX_GPIO_NR(1, 6));
  55
  56
  57 static void cm_fx6_setup_i2c(void)
  58 {
  59         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c0_pads));
  60         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c1_pads));
  61         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c2_pads));
  62 }
  63 #else
  64 static void cm_fx6_setup_i2c(void) { }
  65 #endif
  66
  67 #ifdef CONFIG_USB_EHCI_MX6
  68 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  69                         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  70                         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  71
  72 static int cm_fx6_usb_hub_reset(void)
  73 {
  74         int err;
  75
  76         err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
  77         if (err) {
  78                 printf("USB hub rst gpio request failed: %d\n", err);
  79                 return -1;
  80         }
  81
  82         SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
  83         gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
  84         udelay(10);
  85         gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
  86         mdelay(1);
  87
  88         return 0;
  89 }
  90
  91 static int cm_fx6_init_usb_otg(void)
  92 {
  93         int ret;
  94         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  95
  96         ret = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
  97         if (ret) {
  98                 printf("USB OTG pwr gpio request failed: %d\n", ret);
  99                 return ret;
 100         }
 101
 102         SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
 103         SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
 104                                                 MUX_PAD_CTRL(WEAK_PULLDOWN));
 105         clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
 106         /* disable ext. charger detect, or it'll affect signal quality at dp. */
 107         return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
 108 }
 109
 110 #define MX6_USBNC_BASEADDR      0x2184800
 111 #define USBNC_USB_H1_PWR_POL    (1 << 9)
 112 int board_ehci_hcd_init(int port)
 113 {
 114         u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
 115
 116         switch (port) {
 117         case 0:
 118                 return cm_fx6_init_usb_otg();
 119         case 1:
 120                 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR |
 121                                 MUX_PAD_CTRL(NO_PAD_CTRL));
 122
 123                 /* Set PWR polarity to match power switch's enable polarity */
 124                 setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
 125                 return cm_fx6_usb_hub_reset();
 126         default:
 127                 break;
 128         }
 129
 130         return 0;
 131 }
 132
 133 int board_ehci_power(int port, int on)
 134 {
 135         if (port == 0)
 136                 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
 137
 138         return 0;
 139 }
 140 #endif
 141
 142 #ifdef CONFIG_FEC_MXC
 143 #define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 144                                  PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 145
 146 static int mx6_rgmii_rework(struct phy_device *phydev)
 147 {
 148         unsigned short val;
 149
 150         /* Ar8031 phy SmartEEE feature cause link status generates glitch,
 151          * which cause ethernet link down/up issue, so disable SmartEEE
 152          */
 153         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
 154         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 155         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 156         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 157         val &= ~(0x1 << 8);
 158         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 159
 160         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 161         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 162         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 163         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 164
 165         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 166         val &= 0xffe3;
 167         val |= 0x18;
 168         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 169
 170         /* introduce tx clock delay */
 171         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 172         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 173         val |= 0x0100;
 174         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 175
 176         return 0;
 177 }
 178
 179 int board_phy_config(struct phy_device *phydev)
 180 {
 181         mx6_rgmii_rework(phydev);
 182
 183         if (phydev->drv->config)
 184                 return phydev->drv->config(phydev);
 185
 186         return 0;
 187 }
 188
 189 static iomux_v3_cfg_t const enet_pads[] = {
 190         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 191         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 192         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 193         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 194         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 195         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 196         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 197         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 198         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 199         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 200         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 201         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 202         IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 203         IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 204         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
 205         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
 206                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 207         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 208                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 209         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 210                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 211 };
 212
 213 static int handle_mac_address(void)
 214 {
 215         unsigned char enetaddr[6];
 216         int rc;
 217
 218         rc = eth_getenv_enetaddr("ethaddr", enetaddr);
 219         if (rc)
 220                 return 0;
 221
 222         rc = cl_eeprom_read_mac_addr(enetaddr);
 223         if (rc)
 224                 return rc;
 225
 226         if (!is_valid_ether_addr(enetaddr))
 227                 return -1;
 228
 229         return eth_setenv_enetaddr("ethaddr", enetaddr);
 230 }
 231
 232 int board_eth_init(bd_t *bis)
 233 {
 234         int res = handle_mac_address();
 235         if (res)
 236                 puts("No MAC address found\n");
 237
 238         SETUP_IOMUX_PADS(enet_pads);
 239         /* phy reset */
 240         gpio_direction_output(CM_FX6_ENET_NRST, 0);
 241         udelay(500);
 242         gpio_set_value(CM_FX6_ENET_NRST, 1);
 243         enable_enet_clk(1);
 244         return cpu_eth_init(bis);
 245 }
 246 #endif
 247
 248 #ifdef CONFIG_NAND_MXS
 249 static iomux_v3_cfg_t const nand_pads[] = {
 250         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 251         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 252         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 253         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 254         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 255         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 256         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 257         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 258         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 259         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 260         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 261         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 262         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 263         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 264 };
 265
 266 static void cm_fx6_setup_gpmi_nand(void)
 267 {
 268         SETUP_IOMUX_PADS(nand_pads);
 269         /* Enable clock roots */
 270         enable_usdhc_clk(1, 3);
 271         enable_usdhc_clk(1, 4);
 272
 273         setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
 274                           MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
 275                           MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
 276 }
 277 #else
 278 static void cm_fx6_setup_gpmi_nand(void) {}
 279 #endif
 280
 281 #ifdef CONFIG_FSL_ESDHC
 282 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 283         {USDHC1_BASE_ADDR},
 284         {USDHC2_BASE_ADDR},
 285         {USDHC3_BASE_ADDR},
 286 };
 287
 288 static enum mxc_clock usdhc_clk[3] = {
 289         MXC_ESDHC_CLK,
 290         MXC_ESDHC2_CLK,
 291         MXC_ESDHC3_CLK,
 292 };
 293
 294 int board_mmc_init(bd_t *bis)
 295 {
 296         int i;
 297
 298         cm_fx6_set_usdhc_iomux();
 299         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 300                 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
 301                 usdhc_cfg[i].max_bus_width = 4;
 302                 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 303                 enable_usdhc_clk(1, i);
 304         }
 305
 306         return 0;
 307 }
 308 #endif
 309
 310 #ifdef CONFIG_OF_BOARD_SETUP
 311 void ft_board_setup(void *blob, bd_t *bd)
 312 {
 313         uint8_t enetaddr[6];
 314
 315         /* MAC addr */
 316         if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
 317                 fdt_find_and_setprop(blob, "/fec", "local-mac-address",
 318                                      enetaddr, 6, 1);
 319         }
 320 }
 321 #endif
 322
 323 int board_init(void)
 324 {
 325         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 326         cm_fx6_setup_gpmi_nand();
 327         cm_fx6_setup_i2c();
 328
 329         return 0;
 330 }
 331
 332 int checkboard(void)
 333 {
 334         puts("Board: CM-FX6\n");
 335         return 0;
 336 }
 337
 338 void dram_init_banksize(void)
 339 {
 340         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 341         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 342
 343         switch (gd->ram_size) {
 344         case 0x10000000: /* DDR_16BIT_256MB */
 345                 gd->bd->bi_dram[0].size = 0x10000000;
 346                 gd->bd->bi_dram[1].size = 0;
 347                 break;
 348         case 0x20000000: /* DDR_32BIT_512MB */
 349                 gd->bd->bi_dram[0].size = 0x20000000;
 350                 gd->bd->bi_dram[1].size = 0;
 351                 break;
 352         case 0x40000000:
 353                 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
 354                         gd->bd->bi_dram[0].size = 0x20000000;
 355                         gd->bd->bi_dram[1].size = 0x20000000;
 356                 } else { /* DDR_64BIT_1GB */
 357                         gd->bd->bi_dram[0].size = 0x40000000;
 358                         gd->bd->bi_dram[1].size = 0;
 359                 }
 360                 break;
 361         case 0x80000000: /* DDR_64BIT_2GB */
 362                 gd->bd->bi_dram[0].size = 0x40000000;
 363                 gd->bd->bi_dram[1].size = 0x40000000;
 364                 break;
 365         case 0xEFF00000: /* DDR_64BIT_4GB */
 366                 gd->bd->bi_dram[0].size = 0x70000000;
 367                 gd->bd->bi_dram[1].size = 0x7FF00000;
 368                 break;
 369         }
 370 }
 371
 372 int dram_init(void)
 373 {
 374         gd->ram_size = imx_ddr_size();
 375         switch (gd->ram_size) {
 376         case 0x10000000:
 377         case 0x20000000:
 378         case 0x40000000:
 379         case 0x80000000:
 380                 break;
 381         case 0xF0000000:
 382                 gd->ram_size -= 0x100000;
 383                 break;
 384         default:
 385                 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
 386                 return -1;
 387         }
 388
 389         return 0;
 390 }
 391
 392 u32 get_board_rev(void)
 393 {
 394         return cl_eeprom_get_board_rev();
 395 }
 396