1 // SPDX-License-Identifier: GPL-2.0+
3 * U-Boot board functions for CompuLab CL-SOM-iMX7 module
5 * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
7 * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
17 #include <fsl_esdhc_imx.h>
18 #include <linux/delay.h>
19 #include <power/pmic.h>
20 #include <power/pfuze3000_pmic.h>
21 #include <asm/mach-imx/mxc_i2c.h>
22 #include <asm/mach-imx/iomux-v3.h>
23 #include <asm/arch-mx7/mx7-pins.h>
24 #include <asm/arch-mx7/sys_proto.h>
25 #include <asm/arch-mx7/clock.h>
26 #include "../common/eeprom.h"
29 DECLARE_GLOBAL_DATA_PTR;
31 #ifdef CONFIG_SYS_I2C_MXC
33 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
36 #define CL_SOM_IMX7_GPIO_I2C2_SCL IMX_GPIO_NR(1, 6)
37 #define CL_SOM_IMX7_GPIO_I2C2_SDA IMX_GPIO_NR(1, 7)
39 static struct i2c_pads_info cl_som_imx7_i2c_pad_info2 = {
41 .i2c_mode = MX7D_PAD_GPIO1_IO06__I2C2_SCL |
42 MUX_PAD_CTRL(I2C_PAD_CTRL),
43 .gpio_mode = MX7D_PAD_GPIO1_IO06__GPIO1_IO6 |
44 MUX_PAD_CTRL(I2C_PAD_CTRL),
45 .gp = CL_SOM_IMX7_GPIO_I2C2_SCL,
48 .i2c_mode = MX7D_PAD_GPIO1_IO07__I2C2_SDA |
49 MUX_PAD_CTRL(I2C_PAD_CTRL),
50 .gpio_mode = MX7D_PAD_GPIO1_IO07__GPIO1_IO7 |
51 MUX_PAD_CTRL(I2C_PAD_CTRL),
52 .gp = CL_SOM_IMX7_GPIO_I2C2_SDA,
57 * cl_som_imx7_setup_i2c() - I2C pinmux configuration.
59 static void cl_som_imx7_setup_i2c(void)
61 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &cl_som_imx7_i2c_pad_info2);
63 #else /* !CONFIG_SYS_I2C_MXC */
64 static void cl_som_imx7_setup_i2c(void) {}
65 #endif /* CONFIG_SYS_I2C_MXC */
69 gd->ram_size = imx_ddr_size();
74 #ifdef CONFIG_FSL_ESDHC_IMX
76 #define CL_SOM_IMX7_GPIO_USDHC3_PWR IMX_GPIO_NR(6, 11)
78 static struct fsl_esdhc_cfg cl_som_imx7_usdhc_cfg[3] = {
79 {USDHC1_BASE_ADDR, 0, 4},
83 int board_mmc_init(bd_t *bis)
87 * According to the board_mmc_init() the following map is done:
88 * (U-boot device node) (Physical Port)
92 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
95 cl_som_imx7_usdhc1_pads_set();
96 gpio_request(CL_SOM_IMX7_GPIO_USDHC1_CD, "usdhc1_cd");
97 cl_som_imx7_usdhc_cfg[0].sdhc_clk =
98 mxc_get_clock(MXC_ESDHC_CLK);
101 cl_som_imx7_usdhc3_emmc_pads_set();
102 gpio_request(CL_SOM_IMX7_GPIO_USDHC3_PWR, "usdhc3_pwr");
103 gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 0);
105 gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 1);
106 cl_som_imx7_usdhc_cfg[1].sdhc_clk =
107 mxc_get_clock(MXC_ESDHC3_CLK);
110 printf("Warning: you configured more USDHC controllers "
111 "(%d) than supported by the board\n", i + 1);
115 ret = fsl_esdhc_initialize(bis, &cl_som_imx7_usdhc_cfg[i]);
122 #endif /* CONFIG_FSL_ESDHC_IMX */
124 #ifdef CONFIG_FEC_MXC
126 #define CL_SOM_IMX7_ETH1_PHY_NRST IMX_GPIO_NR(1, 4)
129 * cl_som_imx7_rgmii_rework() - Ethernet PHY configuration.
131 static void cl_som_imx7_rgmii_rework(struct phy_device *phydev)
135 /* Ar8031 phy SmartEEE feature cause link status generates glitch,
136 * which cause ethernet link down/up issue, so disable SmartEEE
138 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
139 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
140 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
141 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
143 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
145 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
146 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
147 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
148 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
150 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
153 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
155 /* introduce tx clock delay */
156 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
157 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
159 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
162 int board_phy_config(struct phy_device *phydev)
164 cl_som_imx7_rgmii_rework(phydev);
166 if (phydev->drv->config)
167 phydev->drv->config(phydev);
173 * cl_som_imx7_handle_mac_address() - set Ethernet MAC address environment.
175 * @env_var: MAC address environment variable
176 * @eeprom_bus: I2C bus of the environment EEPROM
178 * @return: 0 on success, < 0 on failure
180 static int cl_som_imx7_handle_mac_address(char *env_var, uint eeprom_bus)
183 unsigned char enetaddr[6];
185 ret = eth_env_get_enetaddr(env_var, enetaddr);
189 ret = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
193 ret = is_valid_ethaddr(enetaddr);
197 return eth_env_set_enetaddr(env_var, enetaddr);
200 #define CL_SOM_IMX7_FEC_DEV_ID_PRI 0
202 int board_eth_init(bd_t *bis)
204 /* set Ethernet MAC address environment */
205 cl_som_imx7_handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS);
206 /* Ethernet interface pinmux configuration */
207 cl_som_imx7_phy1_rst_pads_set();
208 cl_som_imx7_fec1_pads_set();
210 gpio_request(CL_SOM_IMX7_ETH1_PHY_NRST, "eth1_phy_nrst");
211 gpio_direction_output(CL_SOM_IMX7_ETH1_PHY_NRST, 0);
213 gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1);
214 /* MAC initialization */
215 return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI,
216 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
220 * cl_som_imx7_setup_fec() - Ethernet MAC 1 clock configuration.
221 * - ENET1 reference clock mode select.
222 * - ENET1_TX_CLK output driver is disabled when configured for ALT1.
224 static void cl_som_imx7_setup_fec(void)
226 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
227 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
229 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
230 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
231 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
232 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
234 set_clk_enet(ENET_125MHZ);
236 #else /* !CONFIG_FEC_MXC */
237 static void cl_som_imx7_setup_fec(void) {}
238 #endif /* CONFIG_FEC_MXC */
242 static void cl_som_imx7_spi_init(void)
244 cl_som_imx7_espi1_pads_set();
246 #else /* !CONFIG_SPI */
247 static void cl_som_imx7_spi_init(void) {}
248 #endif /* CONFIG_SPI */
250 int board_early_init_f(void)
252 cl_som_imx7_uart1_pads_set();
253 cl_som_imx7_usb_otg1_pads_set();
260 /* address of boot parameters */
261 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
262 cl_som_imx7_setup_i2c();
263 cl_som_imx7_setup_fec();
264 cl_som_imx7_spi_init();
271 int power_init_board(void)
275 unsigned int reg, rev_id;
277 ret = power_pfuze3000_init(I2C_PMIC);
281 p = pmic_get("PFUZE3000");
286 pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
287 pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
288 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
290 /* disable Low Power Mode during standby mode */
291 pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1);
295 #endif /* CONFIG_POWER */
298 * cl_som_imx7_setup_wdog() - watchdog configuration.
299 * - Output WDOG_B signal to reset external pmic.
300 * - Suspend the watchdog timer during low-power modes.
302 void cl_som_imx7_setup_wdog(void)
304 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
306 cl_som_imx7_wdog_pads_set();
307 set_wdog_reset(wdog);
309 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
310 * since we use PMIC_PWRON to reset the board.
312 clrsetbits_le16(&wdog->wcr, 0, 0x10);
315 int board_late_init(void)
317 env_set("board_name", "CL-SOM-iMX7");
318 cl_som_imx7_setup_wdog();
326 if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
331 printf("Board: CL-SOM-iMX7 in %s mode\n", mode);