board/compulab/cl-som-am57x/spl.c

   1 /*
   2  * SPL data and initialization for CompuLab CL-SOM-AM57x board
   3  *
   4  * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
   5  *
   6  * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <asm/emif.h>
  12 #include <asm/omap_common.h>
  13 #include <asm/arch/sys_proto.h>
  14
  15 static const struct dmm_lisa_map_regs cl_som_am57x_lisa_regs = {
  16         .dmm_lisa_map_3 = 0x80740300,
  17         .is_ma_present  = 0x1
  18 };
  19
  20 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  21 {
  22         /* Disable SDRAM controller EMIF2 for single core SOC */
  23         *dmm_lisa_regs = &cl_som_am57x_lisa_regs;
  24         if (omap_revision() == DRA722_ES1_0) {
  25                 ((struct dmm_lisa_map_regs *) *dmm_lisa_regs)->dmm_lisa_map_3 =
  26                   0x80640100;
  27         }
  28 }
  29
  30 static const struct emif_regs cl_som_am57x_emif1_ddr3_532mhz_emif_regs = {
  31         .sdram_config_init      = 0x61852332,
  32         .sdram_config           = 0x61852332,
  33         .sdram_config2          = 0x00000000,
  34         .ref_ctrl               = 0x000040f1,
  35         .ref_ctrl_final         = 0x00001040,
  36         .sdram_tim1             = 0xeeef36f3,
  37         .sdram_tim2             = 0x348f7fda,
  38         .sdram_tim3             = 0x027f88a8,
  39         .read_idle_ctrl         = 0x00050000,
  40         .zq_config              = 0x1007190b,
  41         .temp_alert_config      = 0x00000000,
  42         .emif_ddr_phy_ctlr_1_init = 0x0034400b,
  43         .emif_ddr_phy_ctlr_1    = 0x0e34400b,
  44         .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  45         .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
  46         .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
  47         .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
  48         .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
  49         .emif_rd_wr_lvl_rmp_win = 0x00000000,
  50         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  51         .emif_rd_wr_lvl_ctl     = 0x00000000,
  52         .emif_rd_wr_exec_thresh = 0x00000305
  53 };
  54
  55 /* Ext phy ctrl regs 1-35 */
  56 static const u32 cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs[] = {
  57         0x10040100,
  58         0x00740074,
  59         0x00780078,
  60         0x007c007c,
  61         0x007b007b,
  62         0x00800080,
  63         0x00360036,
  64         0x00340034,
  65         0x00360036,
  66         0x00350035,
  67         0x00350035,
  68
  69         0x01ff01ff,
  70         0x01ff01ff,
  71         0x01ff01ff,
  72         0x01ff01ff,
  73         0x01ff01ff,
  74
  75         0x00430043,
  76         0x003e003e,
  77         0x004a004a,
  78         0x00470047,
  79         0x00400040,
  80
  81         0x00000000,
  82         0x00600020,
  83         0x40011080,
  84         0x08102040,
  85
  86         0x00400040,
  87         0x00400040,
  88         0x00400040,
  89         0x00400040,
  90         0x00400040,
  91         0x0,
  92         0x0,
  93         0x0,
  94         0x0,
  95         0x0
  96 };
  97
  98 static const struct emif_regs cl_som_am57x_emif2_ddr3_532mhz_emif_regs = {
  99         .sdram_config_init      = 0x61852332,
 100         .sdram_config           = 0x61852332,
 101         .sdram_config2          = 0x00000000,
 102         .ref_ctrl               = 0x000040f1,
 103         .ref_ctrl_final         = 0x00001040,
 104         .sdram_tim1             = 0xeeef36f3,
 105         .sdram_tim2             = 0x348f7fda,
 106         .sdram_tim3             = 0x027f88a8,
 107         .read_idle_ctrl         = 0x00050000,
 108         .zq_config              = 0x1007190b,
 109         .temp_alert_config      = 0x00000000,
 110         .emif_ddr_phy_ctlr_1_init = 0x0034400b,
 111         .emif_ddr_phy_ctlr_1    = 0x0e34400b,
 112         .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
 113         .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
 114         .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
 115         .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
 116         .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
 117         .emif_rd_wr_lvl_rmp_win = 0x00000000,
 118         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
 119         .emif_rd_wr_lvl_ctl     = 0x00000000,
 120         .emif_rd_wr_exec_thresh = 0x00000305
 121 };
 122
 123 static const u32 cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs[] = {
 124         0x10040100,
 125         0x00820082,
 126         0x008b008b,
 127         0x00800080,
 128         0x007e007e,
 129         0x00800080,
 130         0x00370037,
 131         0x00390039,
 132         0x00360036,
 133         0x00370037,
 134         0x00350035,
 135         0x01ff01ff,
 136         0x01ff01ff,
 137         0x01ff01ff,
 138         0x01ff01ff,
 139         0x01ff01ff,
 140         0x00540054,
 141         0x00540054,
 142         0x004e004e,
 143         0x004c004c,
 144         0x00400040,
 145
 146         0x00000000,
 147         0x00600020,
 148         0x40011080,
 149         0x08102040,
 150
 151         0x00400040,
 152         0x00400040,
 153         0x00400040,
 154         0x00400040,
 155         0x00400040,
 156         0x0,
 157         0x0,
 158         0x0,
 159         0x0,
 160         0x0
 161 };
 162
 163 static struct vcores_data cl_som_am57x_volts = {
 164         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 165         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 166         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 167         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 168         .mpu.pmic               = &tps659038,
 169
 170         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 171         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 172         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 173         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 174         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 175         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 176         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 177         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 178         .eve.pmic               = &tps659038,
 179
 180         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 181         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 182         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 183         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 184         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 185         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 186         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 187         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 188         .gpu.pmic               = &tps659038,
 189
 190         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 191         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 192         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 193         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 194         .core.pmic              = &tps659038,
 195
 196         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 197         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 198         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 199         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 200         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 201         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 202         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 203         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 204         .iva.pmic               = &tps659038,
 205 };
 206
 207 void hw_data_init(void)
 208 {
 209         *prcm = &dra7xx_prcm;
 210         *dplls_data = &dra7xx_dplls;
 211         *omap_vcores = &cl_som_am57x_volts;
 212         *ctrl = &dra7xx_ctrl;
 213 }
 214
 215 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 216 {
 217         switch (emif_nr) {
 218         case 1:
 219                 *regs = &cl_som_am57x_emif1_ddr3_532mhz_emif_regs;
 220                 break;
 221         case 2:
 222                 *regs = &cl_som_am57x_emif2_ddr3_532mhz_emif_regs;
 223                 break;
 224         }
 225 }
 226
 227 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 228 {
 229         switch (emif_nr) {
 230         case 1:
 231                 *regs = cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs;
 232                 *size = ARRAY_SIZE(cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs);
 233                 break;
 234         case 2:
 235                 *regs = cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs;
 236                 *size = ARRAY_SIZE(cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs);
 237                 break;
 238         }
 239 }