board/compulab/cl-som-am57x/spl.c

   1 /*
   2  * SPL data and initialization for CompuLab CL-SOM-AM57x board
   3  *
   4  * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
   5  *
   6  * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <asm/emif.h>
  12 #include <asm/omap_common.h>
  13 #include <asm/arch/sys_proto.h>
  14
  15 static const struct dmm_lisa_map_regs cl_som_am57x_lisa_regs = {
  16         .dmm_lisa_map_3 = 0x80740300,
  17         .is_ma_present  = 0x1
  18 };
  19
  20 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  21 {
  22         *dmm_lisa_regs = &cl_som_am57x_lisa_regs;
  23 }
  24
  25 static const struct emif_regs cl_som_am57x_emif1_ddr3_532mhz_emif_regs = {
  26         .sdram_config_init      = 0x61852332,
  27         .sdram_config           = 0x61852332,
  28         .sdram_config2          = 0x00000000,
  29         .ref_ctrl               = 0x000040f1,
  30         .ref_ctrl_final         = 0x00001040,
  31         .sdram_tim1             = 0xeeef36f3,
  32         .sdram_tim2             = 0x348f7fda,
  33         .sdram_tim3             = 0x027f88a8,
  34         .read_idle_ctrl         = 0x00050000,
  35         .zq_config              = 0x1007190b,
  36         .temp_alert_config      = 0x00000000,
  37         .emif_ddr_phy_ctlr_1_init = 0x0034400b,
  38         .emif_ddr_phy_ctlr_1    = 0x0e34400b,
  39         .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  40         .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
  41         .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
  42         .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
  43         .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
  44         .emif_rd_wr_lvl_rmp_win = 0x00000000,
  45         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  46         .emif_rd_wr_lvl_ctl     = 0x00000000,
  47         .emif_rd_wr_exec_thresh = 0x00000305
  48 };
  49
  50 /* Ext phy ctrl regs 1-35 */
  51 static const u32 cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs[] = {
  52         0x10040100,
  53         0x00740074,
  54         0x00780078,
  55         0x007c007c,
  56         0x007b007b,
  57         0x00800080,
  58         0x00360036,
  59         0x00340034,
  60         0x00360036,
  61         0x00350035,
  62         0x00350035,
  63
  64         0x01ff01ff,
  65         0x01ff01ff,
  66         0x01ff01ff,
  67         0x01ff01ff,
  68         0x01ff01ff,
  69
  70         0x00430043,
  71         0x003e003e,
  72         0x004a004a,
  73         0x00470047,
  74         0x00400040,
  75
  76         0x00000000,
  77         0x00600020,
  78         0x40011080,
  79         0x08102040,
  80
  81         0x00400040,
  82         0x00400040,
  83         0x00400040,
  84         0x00400040,
  85         0x00400040,
  86         0x0,
  87         0x0,
  88         0x0,
  89         0x0,
  90         0x0
  91 };
  92
  93 static const struct emif_regs cl_som_am57x_emif2_ddr3_532mhz_emif_regs = {
  94         .sdram_config_init      = 0x61852332,
  95         .sdram_config           = 0x61852332,
  96         .sdram_config2          = 0x00000000,
  97         .ref_ctrl               = 0x000040f1,
  98         .ref_ctrl_final         = 0x00001040,
  99         .sdram_tim1             = 0xeeef36f3,
 100         .sdram_tim2             = 0x348f7fda,
 101         .sdram_tim3             = 0x027f88a8,
 102         .read_idle_ctrl         = 0x00050000,
 103         .zq_config              = 0x1007190b,
 104         .temp_alert_config      = 0x00000000,
 105         .emif_ddr_phy_ctlr_1_init = 0x0034400b,
 106         .emif_ddr_phy_ctlr_1    = 0x0e34400b,
 107         .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
 108         .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
 109         .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
 110         .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
 111         .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
 112         .emif_rd_wr_lvl_rmp_win = 0x00000000,
 113         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
 114         .emif_rd_wr_lvl_ctl     = 0x00000000,
 115         .emif_rd_wr_exec_thresh = 0x00000305
 116 };
 117
 118 static const u32 cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs[] = {
 119         0x10040100,
 120         0x00820082,
 121         0x008b008b,
 122         0x00800080,
 123         0x007e007e,
 124         0x00800080,
 125         0x00370037,
 126         0x00390039,
 127         0x00360036,
 128         0x00370037,
 129         0x00350035,
 130         0x01ff01ff,
 131         0x01ff01ff,
 132         0x01ff01ff,
 133         0x01ff01ff,
 134         0x01ff01ff,
 135         0x00540054,
 136         0x00540054,
 137         0x004e004e,
 138         0x004c004c,
 139         0x00400040,
 140
 141         0x00000000,
 142         0x00600020,
 143         0x40011080,
 144         0x08102040,
 145
 146         0x00400040,
 147         0x00400040,
 148         0x00400040,
 149         0x00400040,
 150         0x00400040,
 151         0x0,
 152         0x0,
 153         0x0,
 154         0x0,
 155         0x0
 156 };
 157
 158 static struct vcores_data cl_som_am57x_volts = {
 159         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 160         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 161         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 162         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 163         .mpu.pmic               = &tps659038,
 164
 165         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 166         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 167         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 168         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 169         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 170         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 171         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 172         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 173         .eve.pmic               = &tps659038,
 174
 175         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 176         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 177         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 178         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 179         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 180         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 181         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 182         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 183         .gpu.pmic               = &tps659038,
 184
 185         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 186         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 187         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 188         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 189         .core.pmic              = &tps659038,
 190
 191         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 192         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 193         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 194         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 195         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 196         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 197         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 198         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 199         .iva.pmic               = &tps659038,
 200 };
 201
 202 void hw_data_init(void)
 203 {
 204         *prcm = &dra7xx_prcm;
 205         *dplls_data = &dra7xx_dplls;
 206         *omap_vcores = &cl_som_am57x_volts;
 207         *ctrl = &dra7xx_ctrl;
 208 }
 209
 210 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 211 {
 212         switch (emif_nr) {
 213         case 1:
 214                 *regs = &cl_som_am57x_emif1_ddr3_532mhz_emif_regs;
 215                 break;
 216         case 2:
 217                 *regs = &cl_som_am57x_emif2_ddr3_532mhz_emif_regs;
 218                 break;
 219         }
 220 }
 221
 222 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 223 {
 224         switch (emif_nr) {
 225         case 1:
 226                 *regs = cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs;
 227                 *size = ARRAY_SIZE(cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs);
 228                 break;
 229         case 2:
 230                 *regs = cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs;
 231                 *size = ARRAY_SIZE(cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs);
 232                 break;
 233         }
 234 }