board/cloudengines/pogo_e02/pogo_e02.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012
   4  * David Purdy <david.c.purdy@gmail.com>
   5  *
   6  * Based on Kirkwood support:
   7  * (C) Copyright 2009
   8  * Marvell Semiconductor <www.marvell.com>
   9  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  10  */
  11
  12 #include <common.h>
  13 #include <init.h>
  14 #include <miiphy.h>
  15 #include <net.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/soc.h>
  18 #include <asm/arch/mpp.h>
  19 #include "pogo_e02.h"
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 int board_early_init_f(void)
  24 {
  25         /*
  26          * default gpio configuration
  27          * There are maximum 64 gpios controlled through 2 sets of registers
  28          * the  below configuration configures mainly initial LED status
  29          */
  30         mvebu_config_gpio(POGO_E02_OE_VAL_LOW,
  31                           POGO_E02_OE_VAL_HIGH,
  32                           POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
  33
  34         /* Multi-Purpose Pins Functionality configuration */
  35         static const u32 kwmpp_config[] = {
  36                 MPP0_NF_IO2,
  37                 MPP1_NF_IO3,
  38                 MPP2_NF_IO4,
  39                 MPP3_NF_IO5,
  40                 MPP4_NF_IO6,
  41                 MPP5_NF_IO7,
  42                 MPP6_SYSRST_OUTn,
  43                 MPP7_GPO,
  44                 MPP8_UART0_RTS,
  45                 MPP9_UART0_CTS,
  46                 MPP10_UART0_TXD,
  47                 MPP11_UART0_RXD,
  48                 MPP12_SD_CLK,
  49                 MPP13_SD_CMD,
  50                 MPP14_SD_D0,
  51                 MPP15_SD_D1,
  52                 MPP16_SD_D2,
  53                 MPP17_SD_D3,
  54                 MPP18_NF_IO0,
  55                 MPP19_NF_IO1,
  56                 MPP29_TSMP9,    /* USB Power Enable */
  57                 MPP48_GPIO,     /* LED green */
  58                 MPP49_GPIO,     /* LED orange */
  59                 0
  60         };
  61         kirkwood_mpp_conf(kwmpp_config, NULL);
  62         return 0;
  63 }
  64
  65 int board_init(void)
  66 {
  67         /* Boot parameters address */
  68         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  69
  70         return 0;
  71 }
  72
  73 #ifdef CONFIG_RESET_PHY_R
  74 /* Configure and initialize PHY */
  75 void reset_phy(void)
  76 {
  77         u16 reg;
  78         u16 devadr;
  79         char *name = "egiga0";
  80
  81         if (miiphy_set_current_dev(name))
  82                 return;
  83
  84         /* command to read PHY dev address */
  85         if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
  86                 printf("Err..(%s) could not read PHY dev address\n", __func__);
  87                 return;
  88         }
  89
  90         /*
  91          * Enable RGMII delay on Tx and Rx for CPU port
  92          * Ref: sec 4.7.2 of chip datasheet
  93          */
  94         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
  95         miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
  96         reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
  97         miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
  98         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
  99
 100         /* reset the phy */
 101         miiphy_reset(name, devadr);
 102
 103         debug("88E1116 Initialized on %s\n", name);
 104 }
 105 #endif /* CONFIG_RESET_PHY_R */