2 * Board initialization for EP93xx
5 * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
8 * Matthias Kaehlcke <matthias <at> kaehlcke.net>
10 * (C) Copyright 2002 2003
11 * Network Audio Technologies, Inc. <www.netaudiotech.com>
12 * Adam Bezanson <bezanson <at> netaudiotech.com>
14 * SPDX-License-Identifier: GPL-2.0+
21 #include <asm/mach-types.h>
22 #include <asm/arch/ep93xx.h>
24 DECLARE_GLOBAL_DATA_PTR;
27 * usb_div: 4, nbyp2: 1, pll2_en: 1
28 * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
29 * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
31 #define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
32 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
33 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
34 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
35 SYSCON_CLKSET2_PLL2_EN | \
36 SYSCON_CLKSET2_NBYP2 | \
37 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
39 #define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
40 SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
41 1 << SMC_BCR_MW_SHIFT)
43 /* delay execution before timers are initialized */
44 static inline void early_udelay(uint32_t usecs)
46 /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
47 register uint32_t loops = (usecs * 1000) / 20;
49 __asm__ volatile ("1:\n"
51 "bne 1b" : "=r" (loops) : "0" (loops));
54 #ifndef CONFIG_EP93XX_NO_FLASH_CFG
55 static void flash_cfg(void)
57 struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
59 writel(SMC_BCR6_VALUE, &smc->bcr6);
68 * Setup PLL2, PPL1 has been set during lowlevel init
70 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
71 writel(CLKSET2_VAL, &syscon->clkset2);
74 * the user's guide recommends to wait at least 1 ms for PLL2 to
79 /* Go to Async mode */
80 __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
81 __asm__ volatile ("orr r0, r0, #0xc0000000");
82 __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
90 /* Machine number, as defined in linux/arch/arm/tools/mach-types */
91 gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
93 /* adress of boot parameters */
94 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
96 /* We have a console */
109 int board_early_init_f(void)
112 * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
115 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
116 writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
120 int board_eth_init(bd_t *bd)
122 return ep93xx_eth_initialize(0, MAC_BASE);
125 static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt,
126 unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS])
128 if (dram_bank_cnt == 1) {
129 dram_bank_base[0] = PHYS_SDRAM_1;
131 /* Table lookup for holes in address space. Maximum memory
132 * for the single SDCS may be up to 256Mb. We start scanning
133 * banks from 1Mb, so it could be up to 128 banks theoretically.
134 * We need at maximum 7 bits for the loockup, 8 slots is
135 * enough for the worst case.
138 unsigned i = dram_bank_cnt / 2;
139 unsigned j = 0x00100000; /* 1 Mb */
140 unsigned *ptbl = tbl;
142 while (!(dram_addr_mask & j)) {
150 for (i = dram_bank_cnt, j = 0;
151 (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
152 unsigned addr = PHYS_SDRAM_1;
156 for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
161 dram_bank_base[j] = addr;
166 /* called in board_init_f (before relocation) */
167 static unsigned dram_init_banksize_int(int print)
170 * Collect information of banks that has been filled during lowlevel
174 unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
175 unsigned dram_total = 0;
176 unsigned dram_bank_size = *(unsigned *)
177 (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE);
178 unsigned dram_addr_mask = *(unsigned *)
179 (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK);
180 unsigned dram_bank_cnt = *(unsigned *)
181 (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT);
183 dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
185 for (i = 0; i < dram_bank_cnt; i++) {
186 gd->bd->bi_dram[i].start = dram_bank_base[i];
187 gd->bd->bi_dram[i].size = dram_bank_size;
188 dram_total += dram_bank_size;
190 for (; i < CONFIG_NR_DRAM_BANKS; i++) {
191 gd->bd->bi_dram[i].start = 0;
192 gd->bd->bi_dram[i].size = 0;
196 printf("DRAM mask: %08x\n", dram_addr_mask);
197 printf("DRAM total %u banks:\n", dram_bank_cnt);
198 printf("bank base-address size\n");
200 if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
201 printf("WARNING! UBoot was configured for %u banks,\n"
202 "but %u has been found. "
203 "Supressing extra memory banks\n",
204 CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
205 dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
208 for (i = 0; i < dram_bank_cnt; i++) {
209 printf(" %u %08x %08x\n",
210 i, dram_bank_base[i], dram_bank_size);
212 printf(" ------------------------------------------\n"
220 int dram_init_banksize(void)
222 dram_init_banksize_int(0);
227 /* called in board_init_f (before relocation) */
230 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
231 unsigned sec_id = readl(SECURITY_EXTENSIONID);
232 unsigned chip_id = readl(&syscon->chipid);
234 printf("CPU: Cirrus Logic ");
235 switch (sec_id & 0x000001FE) {
254 switch (chip_id & 0xF0000000) {
283 printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
285 gd->ram_size = dram_init_banksize_int(1);