2 * Copyright 2004, 2007 Freescale Semiconductor.
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/immap_fsl_pci.h>
33 #include "../common/cadmus.h"
34 #include "../common/eeprom.h"
35 #include "../common/via.h"
37 #if defined(CONFIG_OF_FLAT_TREE)
40 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
41 extern void ddr_enable_ecc(unsigned int dram_size);
44 DECLARE_GLOBAL_DATA_PTR;
46 extern long int spd_sdram(void);
48 void local_bus_init(void);
49 void sdram_init(void);
51 int board_early_init_f (void)
58 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
59 volatile ccsr_gur_t *gur = &immap->im_gur;
60 volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
62 /* PCI slot in USER bits CSR[6:7] by convention. */
63 uint pci_slot = get_pci_slot ();
65 uint cpu_board_rev = get_cpu_board_revision ();
67 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
68 get_board_version (), pci_slot);
70 printf ("CPU Board Revision %d.%d (0x%04x)\n",
71 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
72 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
74 * Initialize local bus.
79 * Fix CPU2 errata: A core hang possible while executing a
80 * msync instruction and a snoopable transaction from an I/O
81 * master tagged to make quick forward progress is present.
83 ecm->eebpcr |= (1 << 16);
86 * Hack TSEC 3 and 4 IO voltages.
88 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
90 ecm->eedr = 0xffffffff; /* clear ecm errors */
91 ecm->eeer = 0xffffffff; /* enable ecm errors */
96 initdram(int board_type)
99 volatile immap_t *immap = (immap_t *)CFG_IMMR;
101 puts("Initializing\n");
103 #if defined(CONFIG_DDR_DLL)
106 * Work around to stabilize DDR DLL MSYNC_IN.
107 * Errata DDR9 seems to have been fixed.
108 * This is now the workaround for Errata DDR11:
109 * Override DLL = 1, Course Adj = 1, Tap Select = 0
112 volatile ccsr_gur_t *gur= &immap->im_gur;
114 gur->ddrdllcr = 0x81000000;
115 asm("sync;isync;msync");
119 dram_size = spd_sdram();
121 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
123 * Initialize and enable DDR ECC.
125 ddr_enable_ecc(dram_size);
128 * SDRAM Initialization
137 * Initialize Local Bus
142 volatile immap_t *immap = (immap_t *)CFG_IMMR;
143 volatile ccsr_gur_t *gur = &immap->im_gur;
144 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
150 get_sys_info(&sysinfo);
151 clkdiv = (lbc->lcrr & 0x0f) * 2;
152 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
154 gur->lbiuiplldcr1 = 0x00078080;
156 gur->lbiuiplldcr0 = 0x7c0f1bf0;
157 } else if (clkdiv == 8) {
158 gur->lbiuiplldcr0 = 0x6c0f1bf0;
159 } else if (clkdiv == 4) {
160 gur->lbiuiplldcr0 = 0x5c0f1bf0;
163 lbc->lcrr |= 0x00030000;
165 asm("sync;isync;msync");
167 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
168 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
172 * Initialize SDRAM memory on the Local Bus.
177 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
180 volatile immap_t *immap = (immap_t *)CFG_IMMR;
181 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
182 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
188 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
191 * Setup SDRAM Base and Option Registers
193 lbc->or2 = CFG_OR2_PRELIM;
196 lbc->br2 = CFG_BR2_PRELIM;
199 lbc->lbcr = CFG_LBC_LBCR;
203 lbc->lsrt = CFG_LBC_LSRT;
204 lbc->mrtpr = CFG_LBC_MRTPR;
208 * MPC8548 uses "new" 15-16 style addressing.
210 cpu_board_rev = get_cpu_board_revision();
211 lsdmr_common = CFG_LBC_LSDMR_COMMON;
212 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
215 * Issue PRECHARGE ALL command.
217 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
220 ppcDcbf((unsigned long) sdram_addr);
224 * Issue 8 AUTO REFRESH commands.
226 for (idx = 0; idx < 8; idx++) {
227 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
230 ppcDcbf((unsigned long) sdram_addr);
235 * Issue 8 MODE-set command.
237 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
240 ppcDcbf((unsigned long) sdram_addr);
244 * Issue NORMAL OP command.
246 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
249 ppcDcbf((unsigned long) sdram_addr);
250 udelay(200); /* Overkill. Must wait > 200 bus cycles */
252 #endif /* enable SDRAM init */
255 #if defined(CFG_DRAM_TEST)
259 uint *pstart = (uint *) CFG_MEMTEST_START;
260 uint *pend = (uint *) CFG_MEMTEST_END;
263 printf("Testing DRAM from 0x%08x to 0x%08x\n",
267 printf("DRAM test phase 1:\n");
268 for (p = pstart; p < pend; p++)
271 for (p = pstart; p < pend; p++) {
272 if (*p != 0xaaaaaaaa) {
273 printf ("DRAM test fails at: %08x\n", (uint) p);
278 printf("DRAM test phase 2:\n");
279 for (p = pstart; p < pend; p++)
282 for (p = pstart; p < pend; p++) {
283 if (*p != 0x55555555) {
284 printf ("DRAM test fails at: %08x\n", (uint) p);
289 printf("DRAM test passed.\n");
294 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
295 /* For some reason the Tundra PCI bridge shows up on itself as a
296 * different device. Work around that by refusing to configure it.
298 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
300 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
301 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
302 {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
303 {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
304 mpc85xx_config_via_usbide, {0,0,0}},
305 {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
306 {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
307 {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
308 mpc85xx_config_via_power, {0,0,0}},
309 {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
313 static struct pci_controller pci1_hose = {
314 config_table: pci_mpc85xxcds_config_table};
315 #endif /* CONFIG_PCI */
318 static struct pci_controller pci2_hose;
319 #endif /* CONFIG_PCI2 */
322 static struct pci_controller pcie1_hose;
323 #endif /* CONFIG_PCIE1 */
325 int first_free_busno=0;
330 volatile immap_t *immap = (immap_t *)CFG_IMMR;
331 volatile ccsr_gur_t *gur = &immap->im_gur;
332 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
333 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
338 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
339 extern void fsl_pci_init(struct pci_controller *hose);
340 struct pci_controller *hose = &pci1_hose;
341 struct pci_config_table *table;
343 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
344 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
345 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
347 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
349 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
351 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
352 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
354 (pci_speed == 33333000) ? "33" :
355 (pci_speed == 66666000) ? "66" : "unknown",
356 pci_clk_sel ? "sync" : "async",
357 pci_agent ? "agent" : "host",
358 pci_arb ? "arbiter" : "external-arbiter"
362 /* outbound memory */
363 pci_set_region(hose->regions + 0,
370 pci_set_region(hose->regions + 1,
375 hose->region_count = 2;
377 /* relocate config table pointers */
378 hose->config_table = \
379 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
380 for (table = hose->config_table; table && table->vendor; table++)
381 table->config_device += gd->reloc_off;
383 hose->first_busno=first_free_busno;
384 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
387 first_free_busno=hose->last_busno+1;
388 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
389 #ifdef CONFIG_PCIX_CHECK
390 if (!(gur->pordevsr & PORDEVSR_PCI)) {
392 if (CONFIG_SYS_CLK_FREQ < 66000000)
393 printf("PCI-X will only work at 66 MHz\n");
395 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
396 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
397 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
401 printf (" PCI: disabled\n");
405 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
410 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
411 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
413 printf (" PCI2: 32 bit, 66 MHz, %s\n",
414 pci2_clk_sel ? "sync" : "async");
416 printf (" PCI2: disabled\n");
420 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
421 #endif /* CONFIG_PCI2 */
425 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
426 extern void fsl_pci_init(struct pci_controller *hose);
427 struct pci_controller *hose = &pcie1_hose;
428 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
430 int pcie_configured = io_sel >= 1;
432 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
433 printf ("\n PCIE connected to slot as %s (base address %x)",
434 pcie_ep ? "End Point" : "Root Complex",
437 if (pci->pme_msg_det) {
438 pci->pme_msg_det = 0xffffffff;
439 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
444 pci_set_region(hose->regions + 0,
448 PCI_REGION_MEM | PCI_REGION_MEMORY);
450 /* outbound memory */
451 pci_set_region(hose->regions + 1,
458 pci_set_region(hose->regions + 2,
464 hose->region_count = 3;
466 hose->first_busno=first_free_busno;
467 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
470 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
472 first_free_busno=hose->last_busno+1;
475 printf (" PCIE: disabled\n");
479 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
484 int last_stage_init(void)
488 /* Change the resistors for the PHY */
489 /* This is needed to get the RGMII working for the 1.3+
491 if (get_board_version() == 0x13) {
492 miiphy_write(CONFIG_TSEC1_NAME,
493 TSEC1_PHY_ADDR, 29, 18);
495 miiphy_read(CONFIG_TSEC1_NAME,
496 TSEC1_PHY_ADDR, 30, &temp);
498 temp = (temp & 0xf03f);
499 temp |= 2 << 9; /* 36 ohm */
500 temp |= 2 << 6; /* 39 ohm */
502 miiphy_write(CONFIG_TSEC1_NAME,
503 TSEC1_PHY_ADDR, 30, temp);
505 miiphy_write(CONFIG_TSEC1_NAME,
506 TSEC1_PHY_ADDR, 29, 3);
508 miiphy_write(CONFIG_TSEC1_NAME,
509 TSEC1_PHY_ADDR, 30, 0x8000);
516 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
518 ft_pci_setup(void *blob, bd_t *bd)
525 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
528 p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
529 debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
534 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len);
537 p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
538 debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);