board/cds/mpc8548cds/init.S

   1 /*
   2  * Copyright 2004, 2007 Freescale Semiconductor.
   3  * Copyright 2002,2003, Motorola Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <ppc_asm.tmpl>
  25 #include <ppc_defs.h>
  26 #include <asm/cache.h>
  27 #include <asm/mmu.h>
  28 #include <config.h>
  29 #include <mpc85xx.h>
  30
  31 #define LAWAR_TRGT_PCI1         0x00000000
  32 #define LAWAR_TRGT_PCI2         0x00100000
  33 #define LAWAR_TRGT_PCIE         0x00200000
  34 #define LAWAR_TRGT_RIO          0x00c00000
  35 #define LAWAR_TRGT_LBC          0x00400000
  36 #define LAWAR_TRGT_DDR          0x00f00000
  37
  38 /*
  39  * TLB0 and TLB1 Entries
  40  *
  41  * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
  42  * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
  43  * these TLB entries are established.
  44  *
  45  * The TLB entries for DDR are dynamically setup in spd_sdram()
  46  * and use TLB1 Entries 8 through 15 as needed according to the
  47  * size of DDR memory.
  48  *
  49  * MAS0: tlbsel, esel, nv
  50  * MAS1: valid, iprot, tid, ts, tsize
  51  * MAS2: epn, sharen, x0, x1, w, i, m, g, e
  52  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  53  */
  54
  55 #define entry_start \
  56         mflr    r1      ;       \
  57         bl      0f      ;
  58
  59 #define entry_end \
  60 0:      mflr    r0      ;       \
  61         mtlr    r1      ;       \
  62         blr             ;
  63
  64
  65         .section        .bootpg, "ax"
  66         .globl  tlb1_entry
  67 tlb1_entry:
  68         entry_start
  69
  70         /*
  71          * Number of TLB0 and TLB1 entries in the following table
  72          */
  73         .long (2f-1f)/16
  74
  75 1:
  76 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
  77         /*
  78          * TLB0         4K      Non-cacheable, guarded
  79          * 0xff700000   4K      Initial CCSRBAR mapping
  80          *
  81          * This ends up at a TLB0 Index==0 entry, and must not collide
  82          * with other TLB0 Entries.
  83          */
  84         .long TLB1_MAS0(0, 0, 0)
  85         .long TLB1_MAS1(1, 0, 0, 0, 0)
  86         .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
  87         .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
  88 #else
  89 #error("Update the number of table entries in tlb1_entry")
  90 #endif
  91
  92         /*
  93          * TLB0         16K     Cacheable, guarded
  94          * Temporary Global data for initialization
  95          *
  96          * Use four 4K TLB0 entries.  These entries must be cacheable
  97          * as they provide the bootstrap memory before the memory
  98          * controler and real memory have been configured.
  99          *
 100          * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
 101          * and must not collide with other TLB0 entries.
 102          */
 103         .long TLB1_MAS0(0, 0, 0)
 104         .long TLB1_MAS1(1, 0, 0, 0, 0)
 105         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
 106                         0,0,0,0,0,0,1,0)
 107         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
 108                         0,0,0,0,0,1,0,1,0,1)
 109
 110         .long TLB1_MAS0(0, 0, 0)
 111         .long TLB1_MAS1(1, 0, 0, 0, 0)
 112         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
 113                         0,0,0,0,0,0,1,0)
 114         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
 115                         0,0,0,0,0,1,0,1,0,1)
 116
 117         .long TLB1_MAS0(0, 0, 0)
 118         .long TLB1_MAS1(1, 0, 0, 0, 0)
 119         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
 120                         0,0,0,0,0,0,1,0)
 121         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
 122                         0,0,0,0,0,1,0,1,0,1)
 123
 124         .long TLB1_MAS0(0, 0, 0)
 125         .long TLB1_MAS1(1, 0, 0, 0, 0)
 126         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
 127                         0,0,0,0,0,0,1,0)
 128         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
 129                         0,0,0,0,0,1,0,1,0,1)
 130
 131
 132         /*
 133          * TLB 0:       16M     Non-cacheable, guarded
 134          * 0xff000000   16M     FLASH
 135          * Out of reset this entry is only 4K.
 136          */
 137         .long TLB1_MAS0(1, 0, 0)
 138         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
 139         .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
 140         .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
 141
 142         /*
 143          * TLB 1:       1G      Non-cacheable, guarded
 144          * 0x80000000   1G      PCI1/PCIE  8,9,a,b
 145          */
 146         .long TLB1_MAS0(1, 1, 0)
 147         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
 148         .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
 149         .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
 150
 151 #ifdef CFG_RIO_MEM_PHYS
 152         /*
 153          * TLB 2:       256M    Non-cacheable, guarded
 154          */
 155         .long TLB1_MAS0(1, 2, 0)
 156         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 157         .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS),
 158                         0,0,0,0,1,0,1,0)
 159         .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1)
 160
 161         /*
 162          * TLB 3:       256M    Non-cacheable, guarded
 163          */
 164         .long TLB1_MAS0(1, 3, 0)
 165         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 166         .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000),
 167                         0,0,0,0,1,0,1,0)
 168         .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000),
 169                         0,0,0,0,0,1,0,1,0,1)
 170 #endif
 171         /*
 172          * TLB 5:       64M     Non-cacheable, guarded
 173          * 0xe000_0000  1M      CCSRBAR
 174          * 0xe200_0000  1M      PCI1 IO
 175          * 0xe210_0000  1M      PCI2 IO
 176          * 0xe300_0000  1M      PCIe IO
 177          */
 178         .long TLB1_MAS0(1, 5, 0)
 179         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 180         .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
 181         .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
 182
 183         /*
 184          * TLB 6:       64M     Cacheable, non-guarded
 185          * 0xf000_0000  64M     LBC SDRAM
 186          */
 187         .long TLB1_MAS0(1, 6, 0)
 188         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 189         .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
 190         .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
 191
 192         /*
 193          * TLB 7:       64M     Non-cacheable, guarded
 194          * 0xf8000000   64M     CADMUS registers, relocated L2SRAM
 195          */
 196         .long TLB1_MAS0(1, 7, 0)
 197         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 198         .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
 199         .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
 200
 201 2:
 202         entry_end
 203
 204 /*
 205  * LAW(Local Access Window) configuration:
 206  *
 207  * 0x0000_0000     0x7fff_ffff     DDR                     2G
 208  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
 209  * 0xa000_0000     0xbfff_ffff     PCIe MEM                512M
 210  * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
 211  * 0xe000_0000     0xe000_ffff     CCSR                    1M
 212  * 0xe200_0000     0xe10f_ffff     PCI1 IO                 1M
 213  * 0xe280_0000     0xe20f_ffff     PCI2 IO                 1M
 214  * 0xe300_0000     0xe30f_ffff     PCIe IO                 1M
 215  * 0xf000_0000     0xf3ff_ffff     SDRAM                   64M
 216  * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
 217  * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
 218  * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
 219  *
 220  * Notes:
 221  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
 222  *    If flash is 8M at default position (last 8M), no LAW needed.
 223  *
 224  * LAW 0 is reserved for boot mapping
 225  */
 226
 227         .section .bootpg, "ax"
 228         .globl  law_entry
 229 law_entry:
 230         entry_start
 231
 232         .long (4f-3f)/8
 233 3:
 234         .long  0
 235         .long  (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
 236
 237 #ifdef CFG_PCI1_MEM_PHYS
 238         .long   (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
 239         .long   LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 240
 241         .long   (CFG_PCI1_IO_PHYS>>12) & 0xfffff
 242         .long   LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
 243 #endif
 244
 245 #ifdef CFG_PCI2_MEM_PHYS
 246         .long   (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
 247         .long   LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 248
 249         .long   (CFG_PCI2_IO_PHYS>>12) & 0xfffff
 250         .long   LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
 251 #endif
 252
 253 #ifdef CFG_PCIE1_MEM_PHYS
 254         .long   (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
 255         .long   LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
 256
 257         .long   (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
 258         .long   LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
 259 #endif
 260
 261         /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 262         .long   (CFG_LBC_CACHE_BASE>>12) & 0xfffff
 263         .long   LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
 264
 265 #ifdef CFG_RIO_MEM_PHYS
 266         .long   (CFG_RIO_MEM_PHYS>>12) & 0xfffff
 267         .long   LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
 268 #endif
 269 4:
 270         entry_end