board/canmb/canmb.c

   1 /*
   2  * (C) Copyright 2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <mpc5xxx.h>
  13 #include <pci.h>
  14
  15 #if defined(CONFIG_MPC5200_DDR)
  16 #include "mt46v16m16-75.h"
  17 #else
  18 #include "mt48lc16m32s2-75.h"
  19 #endif
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #ifndef CONFIG_SYS_RAMBOOT
  24 static void sdram_start (int hi_addr)
  25 {
  26         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  27
  28         /* unlock mode register */
  29         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  30         __asm__ volatile ("sync");
  31
  32         /* precharge all banks */
  33         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  34         __asm__ volatile ("sync");
  35
  36 #if SDRAM_DDR
  37         /* set mode register: extended mode */
  38         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  39         __asm__ volatile ("sync");
  40
  41         /* set mode register: reset DLL */
  42         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  43         __asm__ volatile ("sync");
  44 #endif
  45
  46         /* precharge all banks */
  47         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  48         __asm__ volatile ("sync");
  49
  50         /* auto refresh */
  51         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  52         __asm__ volatile ("sync");
  53
  54         /* set mode register */
  55         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  56         __asm__ volatile ("sync");
  57
  58         /* normal operation */
  59         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  60         __asm__ volatile ("sync");
  61 }
  62 #endif
  63
  64 /*
  65  * ATTENTION: Although partially referenced dram_init does NOT make real use
  66  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  67  *            is something else than 0x00000000.
  68  */
  69
  70 int dram_init(void)
  71 {
  72         ulong dramsize = 0;
  73         ulong dramsize2 = 0;
  74 #ifndef CONFIG_SYS_RAMBOOT
  75         ulong test1, test2;
  76
  77         /* setup SDRAM chip selects */
  78         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
  79         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
  80         __asm__ volatile ("sync");
  81
  82         /* setup config registers */
  83         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
  84         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
  85         __asm__ volatile ("sync");
  86
  87 #if SDRAM_DDR
  88         /* set tap delay */
  89         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
  90         __asm__ volatile ("sync");
  91 #endif
  92
  93         /* find RAM size using SDRAM CS0 only */
  94         sdram_start(0);
  95         test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  96         sdram_start(1);
  97         test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  98         if (test1 > test2) {
  99                 sdram_start(0);
 100                 dramsize = test1;
 101         } else {
 102                 dramsize = test2;
 103         }
 104
 105         /* memory smaller than 1MB is impossible */
 106         if (dramsize < (1 << 20)) {
 107                 dramsize = 0;
 108         }
 109
 110         /* set SDRAM CS0 size according to the amount of RAM found */
 111         if (dramsize > 0) {
 112                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 113         } else {
 114                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 115         }
 116
 117         /* let SDRAM CS1 start right after CS0 */
 118         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 119
 120         /* find RAM size using SDRAM CS1 only */
 121         if (!dramsize)
 122                 sdram_start(0);
 123         test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 124         if (!dramsize) {
 125                 sdram_start(1);
 126                 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 127         }
 128         if (test1 > test2) {
 129                 sdram_start(0);
 130                 dramsize2 = test1;
 131         } else {
 132                 dramsize2 = test2;
 133         }
 134
 135         /* memory smaller than 1MB is impossible */
 136         if (dramsize2 < (1 << 20)) {
 137                 dramsize2 = 0;
 138         }
 139
 140         /* set SDRAM CS1 size according to the amount of RAM found */
 141         if (dramsize2 > 0) {
 142                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 143                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 144         } else {
 145                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 146         }
 147
 148 #else /* CONFIG_SYS_RAMBOOT */
 149
 150         /* retrieve size of memory connected to SDRAM CS0 */
 151         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 152         if (dramsize >= 0x13) {
 153                 dramsize = (1 << (dramsize - 0x13)) << 20;
 154         } else {
 155                 dramsize = 0;
 156         }
 157
 158         /* retrieve size of memory connected to SDRAM CS1 */
 159         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 160         if (dramsize2 >= 0x13) {
 161                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 162         } else {
 163                 dramsize2 = 0;
 164         }
 165
 166 #endif /* CONFIG_SYS_RAMBOOT */
 167
 168         gd->ram_size = dramsize + dramsize2;
 169
 170         return 0;
 171 }
 172
 173 int checkboard (void)
 174 {
 175         puts ("Board: CANMB\n");
 176         return 0;
 177 }
 178
 179 int board_early_init_r (void)
 180 {
 181         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 182         *(vu_long *)MPC5XXX_BOOTCS_START =
 183         *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
 184         *(vu_long *)MPC5XXX_BOOTCS_STOP =
 185         *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
 186         return 0;
 187 }