1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007 - 2013 Tensilica Inc.
4 * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
11 #include <dm/platform_data/net_ethoc.h>
13 #include <linux/ctype.h>
14 #include <linux/string.h>
15 #include <linux/stringify.h>
16 #include <asm/global_data.h>
18 DECLARE_GLOBAL_DATA_PTR;
21 * Check board idendity.
22 * (Print information about the board to stdout.)
26 #if defined(CONFIG_XTFPGA_LX60)
27 const char *board = "XT_AV60";
28 const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / ";
29 #elif defined(CONFIG_XTFPGA_LX110)
30 const char *board = "XT_AV110";
31 const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / ";
32 #elif defined(CONFIG_XTFPGA_LX200)
33 const char *board = "XT_AV200";
34 const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / ";
35 #elif defined(CONFIG_XTFPGA_ML605)
36 const char *board = "XT_ML605";
37 const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / ";
38 #elif defined(CONFIG_XTFPGA_KC705)
39 const char *board = "XT_KC705";
40 const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / ";
42 const char *board = "<unknown>";
43 const char *description = "";
48 printf("Board: %s: %sTensilica bitstream\n", board, description);
52 int board_postclk_init(void)
55 * Obtain CPU clock frequency from board and cache in global
56 * data structure (Hz). Return 0 on success (OK to continue),
57 * else non-zero (hang).
60 #ifdef CONFIG_SYS_FPGAREG_FREQ
61 gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
63 /* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
64 gd->cpu_clk = 50000000UL;
70 * Miscellaneous late initializations.
71 * The environment has been set up, so we can set the Ethernet address.
78 * Initialize ethernet environment variables and board info.
79 * Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6.
82 char *s = env_get("ethaddr");
85 char s[] = __stringify(CONFIG_ETHBASE);
86 x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW)
88 sprintf(&s[15], "%02x", x);
89 env_set("ethaddr", s);
91 #endif /* CONFIG_CMD_NET */
96 U_BOOT_DEVICE(sysreset) = {
97 .name = "xtfpga_sysreset",
100 static struct ethoc_eth_pdata ethoc_pdata = {
102 .iobase = CONFIG_SYS_ETHOC_BASE,
104 .packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR,
107 U_BOOT_DEVICE(ethoc) = {
109 .platdata = ðoc_pdata,