board/broadcom/bcmns3/ns3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2020 Broadcom.
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <fdt_support.h>
   9 #include <asm/io.h>
  10 #include <asm/gic-v3.h>
  11 #include <asm/system.h>
  12 #include <asm/armv8/mmu.h>
  13 #include <asm/arch-bcmns3/bl33_info.h>
  14 #include <dt-bindings/memory/bcm-ns3-mc.h>
  15 #include <broadcom/chimp.h>
  16
  17 /* Default reset-level = 3 and strap-val = 0 */
  18 #define L3_RESET        30
  19
  20 #define BANK_OFFSET(bank)      ((u64)BCM_NS3_DDR_INFO_BASE + 8 + ((bank) * 16))
  21
  22 /*
  23  * ns3_dram_bank - DDR bank details
  24  *
  25  * @start: DDR bank start address
  26  * @len: DDR bank length
  27  */
  28 struct ns3_dram_bank {
  29         u64 start[BCM_NS3_MAX_NR_BANKS];
  30         u64 len[BCM_NS3_MAX_NR_BANKS];
  31 };
  32
  33 /*
  34  * ns3_dram_hdr - DDR header info
  35  *
  36  * @sig: DDR info signature
  37  * @bank: DDR bank details
  38  */
  39 struct ns3_dram_hdr {
  40         u32 sig;
  41         struct ns3_dram_bank bank;
  42 };
  43
  44 static struct mm_region ns3_mem_map[] = {
  45         {
  46                 .virt = 0x0UL,
  47                 .phys = 0x0UL,
  48                 .size = 0x80000000UL,
  49                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  50                          PTE_BLOCK_NON_SHARE |
  51                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  52         }, {
  53                 .virt = BCM_NS3_MEM_START,
  54                 .phys = BCM_NS3_MEM_START,
  55                 .size = BCM_NS3_MEM_LEN,
  56                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  57                          PTE_BLOCK_INNER_SHARE
  58         }, {
  59                 .virt = BCM_NS3_BANK_1_MEM_START,
  60                 .phys = BCM_NS3_BANK_1_MEM_START,
  61                 .size = BCM_NS3_BANK_1_MEM_LEN,
  62                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  63                          PTE_BLOCK_INNER_SHARE
  64         }, {
  65                 /* List terminator */
  66                 0,
  67         }
  68 };
  69
  70 struct mm_region *mem_map = ns3_mem_map;
  71
  72 DECLARE_GLOBAL_DATA_PTR;
  73
  74 /*
  75  * Force the bl33_info to the data-section, as .bss will not be valid
  76  * when save_boot_params is invoked.
  77  */
  78 struct bl33_info *bl33_info __section(".data");
  79
  80 /*
  81  * Run modulo 256 checksum calculation and return the calculated checksum
  82  */
  83 static u8 checksum_calc(u8 *p, unsigned int len)
  84 {
  85         unsigned int i;
  86         u8 chksum = 0;
  87
  88         for (i = 0; i < len; i++)
  89                 chksum += p[i];
  90
  91         return chksum;
  92 }
  93
  94 /*
  95  * This function parses the memory layout information from a reserved area in
  96  * DDR, and then fix up the FDT before passing it to Linux.
  97  *
  98  * In the case of error, do nothing and the default memory layout in DT will
  99  * be used
 100  */
 101 static int mem_info_parse_fixup(void *fdt)
 102 {
 103         struct ns3_dram_hdr hdr;
 104         u32 *p32, i, nr_banks;
 105         u64 *p64;
 106
 107         /* validate signature */
 108         p32 = (u32 *)BCM_NS3_DDR_INFO_BASE;
 109         hdr.sig = *p32;
 110         if (hdr.sig != BCM_NS3_DDR_INFO_SIG) {
 111                 printf("DDR info signature 0x%x invalid\n", hdr.sig);
 112                 return -EINVAL;
 113         }
 114
 115         /* run checksum test to validate data  */
 116         if (checksum_calc((u8 *)p32, BCM_NS3_DDR_INFO_LEN) != 0) {
 117                 printf("Checksum on DDR info failed\n");
 118                 return -EINVAL;
 119         }
 120
 121         /* parse information for each bank */
 122         nr_banks = 0;
 123         for (i = 0; i < BCM_NS3_MAX_NR_BANKS; i++) {
 124                 /* skip banks with a length of zero */
 125                 p64 = (u64 *)BANK_OFFSET(i);
 126                 if (*(p64 + 1) == 0)
 127                         continue;
 128
 129                 hdr.bank.start[i] = *p64;
 130                 hdr.bank.len[i] = *(p64 + 1);
 131
 132                 printf("mem[%u] 0x%llx - 0x%llx\n", i, hdr.bank.start[i],
 133                        hdr.bank.start[i] + hdr.bank.len[i] - 1);
 134                 nr_banks++;
 135         }
 136
 137         if (!nr_banks) {
 138                 printf("No DDR banks detected\n");
 139                 return -ENOMEM;
 140         }
 141
 142         return fdt_fixup_memory_banks(fdt, hdr.bank.start, hdr.bank.len,
 143                                       nr_banks);
 144 }
 145
 146 int board_init(void)
 147 {
 148         /* Setup memory using "memory" node from DTB */
 149         if (fdtdec_setup_mem_size_base() != 0)
 150                 return -EINVAL;
 151         fdtdec_setup_memory_banksize();
 152
 153         if (bl33_info->version != BL33_INFO_VERSION)
 154                 printf("*** warning: ATF BL31 and U-Boot not in sync! ***\n");
 155
 156         return 0;
 157 }
 158
 159 int board_late_init(void)
 160 {
 161         return 0;
 162 }
 163
 164 int dram_init(void)
 165 {
 166         /*
 167          * Mark ram base as the last 16MB of 2GB DDR, which is 0xFF00_0000.
 168          * So that relocation happens with in the last 16MB memory.
 169          */
 170         gd->ram_base = (phys_size_t)(BCM_NS3_MEM_END - SZ_16M);
 171         gd->ram_size = (unsigned long)SZ_16M;
 172
 173         return 0;
 174 }
 175
 176 int dram_init_banksize(void)
 177 {
 178         gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M);
 179         gd->bd->bi_dram[0].size = SZ_16M;
 180
 181         return 0;
 182 }
 183
 184 /* Limit RAM used by U-Boot to the DDR first bank End region */
 185 ulong board_get_usable_ram_top(ulong total_size)
 186 {
 187         return BCM_NS3_MEM_END;
 188 }
 189
 190 void reset_cpu(ulong level)
 191 {
 192         u32 reset_level, strap_val;
 193
 194         /* Default reset type is L3 reset */
 195         if (!level) {
 196                 /*
 197                  * Encoding: U-Boot reset command expects decimal argument,
 198                  * Boot strap val: Bits[3:0]
 199                  * reset level: Bits[7:4]
 200                  */
 201                 strap_val = L3_RESET % 10;
 202                 level = L3_RESET / 10;
 203                 reset_level = level % 10;
 204                 psci_system_reset2(reset_level, strap_val);
 205         } else {
 206                 /* U-Boot cmd "reset" with any arg will trigger L1 reset */
 207                 psci_system_reset();
 208         }
 209 }
 210
 211 #ifdef CONFIG_OF_BOARD_SETUP
 212 int ft_board_setup(void *fdt, struct bd_info *bd)
 213 {
 214         u32 chimp_hs = CHIMP_HANDSHAKE_WAIT_TIMEOUT;
 215
 216         gic_lpi_tables_init();
 217
 218         /*
 219          * Check for chimp handshake status.
 220          * Zero timeout value will actually fall to default timeout.
 221          *
 222          * System boot is independent of chimp handshake.
 223          * chimp handshake failure is not a catastrophic error.
 224          * Hence continue booting if chimp handshake fails.
 225          */
 226         chimp_handshake_status_optee(0, &chimp_hs);
 227         if (chimp_hs == CHIMP_HANDSHAKE_SUCCESS)
 228                 printf("ChiMP handshake successful\n");
 229         else
 230                 printf("ERROR: ChiMP handshake status 0x%x\n", chimp_hs);
 231
 232         return mem_info_parse_fixup(fdt);
 233 }
 234 #endif /* CONFIG_OF_BOARD_SETUP */