1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/sys_proto.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <linux/errno.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/mach-imx/sata.h>
20 #include <asm/mach-imx/spi.h>
21 #include <asm/mach-imx/boot_mode.h>
22 #include <asm/mach-imx/video.h>
24 #include <fsl_esdhc_imx.h>
28 #include <asm/arch/crm_regs.h>
29 #include <asm/arch/mxc_hdmi.h>
33 #include <usb/ehci-ci.h>
35 DECLARE_GLOBAL_DATA_PTR;
36 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
38 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
39 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
40 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
43 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
44 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
49 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
50 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
52 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
53 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
55 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
56 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
57 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
59 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
60 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
63 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
65 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
67 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
71 gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
76 static iomux_v3_cfg_t const uart1_pads[] = {
77 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
78 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
81 static iomux_v3_cfg_t const uart2_pads[] = {
82 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
83 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
86 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
89 static struct i2c_pads_info i2c_pad_info0 = {
91 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
92 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
93 .gp = IMX_GPIO_NR(3, 21)
96 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
97 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
98 .gp = IMX_GPIO_NR(3, 28)
102 /* I2C2 Camera, MIPI */
103 static struct i2c_pads_info i2c_pad_info1 = {
105 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
106 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
107 .gp = IMX_GPIO_NR(4, 12)
110 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
111 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
112 .gp = IMX_GPIO_NR(4, 13)
116 /* I2C3, J15 - RGB connector */
117 static struct i2c_pads_info i2c_pad_info2 = {
119 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
120 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
121 .gp = IMX_GPIO_NR(1, 5)
124 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
125 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
126 .gp = IMX_GPIO_NR(7, 11)
130 static iomux_v3_cfg_t const usdhc2_pads[] = {
131 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 static iomux_v3_cfg_t const usdhc3_pads[] = {
140 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
149 static iomux_v3_cfg_t const usdhc4_pads[] = {
150 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
156 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
159 static iomux_v3_cfg_t const enet_pads1[] = {
160 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
161 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
162 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
163 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
164 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
165 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
166 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
167 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
168 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
169 /* pin 35 - 1 (PHY_AD2) on reset */
170 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
171 /* pin 32 - 1 - (MODE0) all */
172 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
173 /* pin 31 - 1 - (MODE1) all */
174 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
175 /* pin 28 - 1 - (MODE2) all */
176 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
177 /* pin 27 - 1 - (MODE3) all */
178 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
179 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
180 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
181 /* pin 42 PHY nRST */
182 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
183 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
186 static iomux_v3_cfg_t const enet_pads2[] = {
187 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
188 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
189 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
190 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
191 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
192 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
195 static iomux_v3_cfg_t const misc_pads[] = {
196 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
197 MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
198 MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
199 /* OTG Power enable */
200 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM),
203 /* wl1271 pads on nitrogen6x */
204 static iomux_v3_cfg_t const wl12xx_pads[] = {
205 (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
206 | MUX_PAD_CTRL(WEAK_PULLDOWN),
207 (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
208 | MUX_PAD_CTRL(OUTPUT_40OHM),
209 (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
210 | MUX_PAD_CTRL(OUTPUT_40OHM),
212 #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
213 #define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
214 #define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16)
216 /* Button assignments for J14 */
217 static iomux_v3_cfg_t const button_pads[] = {
219 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
221 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
222 /* Labelled Search (mapped to Power under Android) */
223 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
225 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
227 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
229 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
232 static void setup_iomux_enet(void)
234 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
235 gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
236 gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
237 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
238 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
239 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
240 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
241 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
242 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
244 /* Need delay 10ms according to KSZ9021 spec */
246 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
247 gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
249 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
250 udelay(100); /* Wait 100 us before using mii interface */
253 static iomux_v3_cfg_t const usb_pads[] = {
254 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
257 static void setup_iomux_uart(void)
259 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
260 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
263 #ifdef CONFIG_USB_EHCI_MX6
264 int board_ehci_hcd_init(int port)
266 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
269 gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
271 gpio_set_value(IMX_GPIO_NR(7, 12), 1);
276 int board_ehci_power(int port, int on)
280 gpio_set_value(GP_USB_OTG_PWR, on);
286 #ifdef CONFIG_FSL_ESDHC_IMX
287 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
292 int board_mmc_getcd(struct mmc *mmc)
294 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
295 int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
298 gpio_direction_input(gp_cd);
299 return !gpio_get_value(gp_cd);
302 int board_mmc_init(bd_t *bis)
307 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
308 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
310 usdhc_cfg[0].max_bus_width = 4;
311 usdhc_cfg[1].max_bus_width = 4;
313 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
316 imx_iomux_v3_setup_multiple_pads(
317 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
320 imx_iomux_v3_setup_multiple_pads(
321 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
324 printf("Warning: you configured more USDHC controllers"
325 "(%d) then supported by the board (%d)\n",
326 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
330 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
339 #ifdef CONFIG_MXC_SPI
340 int board_spi_cs_gpio(unsigned bus, unsigned cs)
342 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
345 static iomux_v3_cfg_t const ecspi1_pads[] = {
347 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
348 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
349 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
350 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
353 static void setup_spi(void)
355 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
356 ARRAY_SIZE(ecspi1_pads));
360 int board_phy_config(struct phy_device *phydev)
362 /* min rx data delay */
363 ksz9021_phy_extended_write(phydev,
364 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
365 /* min tx data delay */
366 ksz9021_phy_extended_write(phydev,
367 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
368 /* max rx/tx clock delay, min rx/tx control */
369 ksz9021_phy_extended_write(phydev,
370 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
371 if (phydev->drv->config)
372 phydev->drv->config(phydev);
377 int board_eth_init(bd_t *bis)
379 uint32_t base = IMX_FEC_BASE;
380 struct mii_dev *bus = NULL;
381 struct phy_device *phydev = NULL;
386 #ifdef CONFIG_FEC_MXC
387 bus = fec_get_miibus(base, -1);
390 /* scan phy 4,5,6,7 */
391 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
396 printf("using phy at %d\n", phydev->addr);
397 ret = fec_probe(bis, -1, base, bus, phydev);
403 /* For otg ethernet*/
404 usb_eth_initialize(bis);
415 static void setup_buttons(void)
417 imx_iomux_v3_setup_multiple_pads(button_pads,
418 ARRAY_SIZE(button_pads));
421 #if defined(CONFIG_VIDEO_IPUV3)
423 static iomux_v3_cfg_t const backlight_pads[] = {
424 /* Backlight on RGB connector: J15 */
425 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
426 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
428 /* Backlight on LVDS connector: J6 */
429 MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
430 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
433 static iomux_v3_cfg_t const rgb_pads[] = {
434 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
435 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
436 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
437 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
438 MX6_PAD_DI0_PIN4__GPIO4_IO20,
439 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
440 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
441 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
442 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
443 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
444 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
445 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
446 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
447 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
448 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
449 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
450 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
451 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
452 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
453 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
454 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
455 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
456 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
457 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
458 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
459 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
460 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
461 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
462 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
465 static void do_enable_hdmi(struct display_info_t const *dev)
467 imx_enable_hdmi_phy();
470 static int detect_i2c(struct display_info_t const *dev)
472 return ((0 == i2c_set_bus_num(dev->bus))
474 (0 == i2c_probe(dev->addr)));
477 static void enable_lvds(struct display_info_t const *dev)
479 struct iomuxc *iomux = (struct iomuxc *)
481 u32 reg = readl(&iomux->gpr[2]);
482 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
483 writel(reg, &iomux->gpr[2]);
484 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
487 static void enable_lvds_jeida(struct display_info_t const *dev)
489 struct iomuxc *iomux = (struct iomuxc *)
491 u32 reg = readl(&iomux->gpr[2]);
492 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
493 |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
494 writel(reg, &iomux->gpr[2]);
495 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
498 static void enable_rgb(struct display_info_t const *dev)
500 imx_iomux_v3_setup_multiple_pads(
502 ARRAY_SIZE(rgb_pads));
503 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
506 struct display_info_t const displays[] = {{
509 .pixfmt = IPU_PIX_FMT_RGB24,
510 .detect = detect_i2c,
511 .enable = do_enable_hdmi,
525 .vmode = FB_VMODE_NONINTERLACED
529 .pixfmt = IPU_PIX_FMT_RGB24,
531 .enable = enable_lvds_jeida,
545 .vmode = FB_VMODE_NONINTERLACED
549 .pixfmt = IPU_PIX_FMT_RGB24,
551 .enable = enable_lvds,
553 .name = "LDB-WXGA-S",
565 .vmode = FB_VMODE_NONINTERLACED
569 .pixfmt = IPU_PIX_FMT_LVDS666,
570 .detect = detect_i2c,
571 .enable = enable_lvds,
573 .name = "Hannstar-XGA",
585 .vmode = FB_VMODE_NONINTERLACED
589 .pixfmt = IPU_PIX_FMT_LVDS666,
591 .enable = enable_lvds,
597 .pixclock = 15385, /* ~65MHz */
605 .vmode = FB_VMODE_NONINTERLACED
609 .pixfmt = IPU_PIX_FMT_LVDS666,
610 .detect = detect_i2c,
611 .enable = enable_lvds,
613 .name = "wsvga-lvds",
625 .vmode = FB_VMODE_NONINTERLACED
629 .pixfmt = IPU_PIX_FMT_RGB666,
630 .detect = detect_i2c,
631 .enable = enable_rgb,
645 .vmode = FB_VMODE_NONINTERLACED
649 .pixfmt = IPU_PIX_FMT_RGB666,
651 .enable = enable_rgb,
665 .vmode = FB_VMODE_NONINTERLACED
669 .pixfmt = IPU_PIX_FMT_LVDS666,
670 .detect = detect_i2c,
671 .enable = enable_lvds,
673 .name = "amp1024x600",
685 .vmode = FB_VMODE_NONINTERLACED
689 .pixfmt = IPU_PIX_FMT_LVDS666,
691 .enable = enable_lvds,
705 .vmode = FB_VMODE_NONINTERLACED
709 .pixfmt = IPU_PIX_FMT_RGB666,
710 .detect = detect_i2c,
711 .enable = enable_rgb,
725 .vmode = FB_VMODE_NONINTERLACED
729 .pixfmt = IPU_PIX_FMT_RGB24,
731 .enable = enable_rgb,
745 .vmode = FB_VMODE_NONINTERLACED
747 size_t display_count = ARRAY_SIZE(displays);
749 int board_cfb_skip(void)
751 return NULL != env_get("novideo");
754 static void setup_display(void)
756 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
757 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
762 /* Turn on LDB0,IPU,IPU DI0 clocks */
763 reg = __raw_readl(&mxc_ccm->CCGR3);
764 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
765 writel(reg, &mxc_ccm->CCGR3);
767 /* set LDB0, LDB1 clk select to 011/011 */
768 reg = readl(&mxc_ccm->cs2cdr);
769 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
770 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
771 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
772 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
773 writel(reg, &mxc_ccm->cs2cdr);
775 reg = readl(&mxc_ccm->cscmr2);
776 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
777 writel(reg, &mxc_ccm->cscmr2);
779 reg = readl(&mxc_ccm->chsccdr);
780 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
781 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
782 writel(reg, &mxc_ccm->chsccdr);
784 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
785 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
786 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
787 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
788 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
789 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
790 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
791 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
792 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
793 writel(reg, &iomux->gpr[2]);
795 reg = readl(&iomux->gpr[3]);
796 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
797 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
798 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
799 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
800 writel(reg, &iomux->gpr[3]);
802 /* backlights off until needed */
803 imx_iomux_v3_setup_multiple_pads(backlight_pads,
804 ARRAY_SIZE(backlight_pads));
805 gpio_direction_input(LVDS_BACKLIGHT_GP);
806 gpio_direction_input(RGB_BACKLIGHT_GP);
810 static iomux_v3_cfg_t const init_pads[] = {
811 /* SGTL5000 sys_mclk */
812 NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
814 /* J5 - Camera MCLK */
815 NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
817 /* wl1271 pads on nitrogen6x */
818 /* WL12XX_WL_IRQ_GP */
819 NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
820 /* WL12XX_WL_ENABLE_GP */
821 NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
822 /* WL12XX_BT_ENABLE_GP */
823 NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
825 NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
826 NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
827 NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
828 NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
829 NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
832 #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
834 static unsigned gpios_out_low[] = {
836 IMX_GPIO_NR(6, 15), /* disable wireless */
837 IMX_GPIO_NR(6, 16), /* disable bluetooth */
838 IMX_GPIO_NR(3, 22), /* disable USB otg power */
839 IMX_GPIO_NR(2, 5), /* ov5640 mipi camera reset */
840 IMX_GPIO_NR(1, 8), /* ov5642 reset */
843 static unsigned gpios_out_high[] = {
844 IMX_GPIO_NR(1, 6), /* ov5642 powerdown */
845 IMX_GPIO_NR(6, 9), /* ov5640 mipi camera power down */
848 static void set_gpios(unsigned *p, int cnt, int val)
852 for (i = 0; i < cnt; i++)
853 gpio_direction_output(*p++, val);
856 int board_early_init_f(void)
860 set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
861 set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
862 gpio_direction_input(WL12XX_WL_IRQ_GP);
864 imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
865 imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
868 #if defined(CONFIG_VIDEO_IPUV3)
875 * Do not overwrite the console
876 * Use always serial for U-Boot console
878 int overwrite_console(void)
885 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
887 clrsetbits_le32(&iomuxc_regs->gpr[1],
888 IOMUXC_GPR1_OTG_ID_MASK,
889 IOMUXC_GPR1_OTG_ID_GPIO1);
891 imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
893 /* address of boot parameters */
894 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
896 #ifdef CONFIG_MXC_SPI
899 imx_iomux_v3_setup_multiple_pads(
900 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
901 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
902 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
903 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
914 if (gpio_get_value(WL12XX_WL_IRQ_GP))
915 puts("Board: Nitrogen6X\n");
917 puts("Board: SABRE Lite\n");
928 static struct button_key const buttons[] = {
929 {"back", IMX_GPIO_NR(2, 2), 'B'},
930 {"home", IMX_GPIO_NR(2, 4), 'H'},
931 {"menu", IMX_GPIO_NR(2, 1), 'M'},
932 {"search", IMX_GPIO_NR(2, 3), 'S'},
933 {"volup", IMX_GPIO_NR(7, 13), 'V'},
934 {"voldown", IMX_GPIO_NR(4, 5), 'v'},
938 * generate a null-terminated string containing the buttons pressed
939 * returns number of keys pressed
941 static int read_keys(char *buf)
943 int i, numpressed = 0;
944 for (i = 0; i < ARRAY_SIZE(buttons); i++) {
945 if (!gpio_get_value(buttons[i].gpnum))
946 buf[numpressed++] = buttons[i].ident;
948 buf[numpressed] = '\0';
952 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
954 char envvalue[ARRAY_SIZE(buttons)+1];
955 int numpressed = read_keys(envvalue);
956 env_set("keybd", envvalue);
957 return numpressed == 0;
962 "Tests for keypresses, sets 'keybd' environment variable",
963 "Returns 0 (true) to shell if key is pressed."
966 #ifdef CONFIG_PREBOOT
967 static char const kbd_magic_prefix[] = "key_magic";
968 static char const kbd_command_prefix[] = "key_cmd";
970 static void preboot_keys(void)
973 char keypress[ARRAY_SIZE(buttons)+1];
974 numpressed = read_keys(keypress);
976 char *kbd_magic_keys = env_get("magic_keys");
979 * loop over all magic keys
981 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
983 char magic[sizeof(kbd_magic_prefix) + 1];
984 sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
985 keys = env_get(magic);
987 if (!strcmp(keys, keypress))
992 char cmd_name[sizeof(kbd_command_prefix) + 1];
994 sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
995 cmd = env_get(cmd_name);
997 env_set("preboot", cmd);
1005 #ifdef CONFIG_CMD_BMODE
1006 static const struct boot_mode board_boot_modes[] = {
1007 /* 4 bit bus width */
1008 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
1009 {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
1014 int misc_init_r(void)
1016 #ifdef CONFIG_PREBOOT
1020 #ifdef CONFIG_CMD_BMODE
1021 add_board_boot_modes(board_boot_modes);
1023 env_set_hex("reset_cause", get_imx_reset_cause());