board/boundary/nitrogen6x/nitrogen6x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  */
   6
   7 #include <common.h>
   8 #include <env.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <malloc.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <linux/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/mxc_i2c.h>
  20 #include <asm/mach-imx/sata.h>
  21 #include <asm/mach-imx/spi.h>
  22 #include <asm/mach-imx/boot_mode.h>
  23 #include <asm/mach-imx/video.h>
  24 #include <mmc.h>
  25 #include <fsl_esdhc_imx.h>
  26 #include <micrel.h>
  27 #include <miiphy.h>
  28 #include <netdev.h>
  29 #include <asm/arch/crm_regs.h>
  30 #include <asm/arch/mxc_hdmi.h>
  31 #include <i2c.h>
  32 #include <input.h>
  33 #include <netdev.h>
  34 #include <usb/ehci-ci.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  38
  39 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  40         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  41         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  42
  43 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  44         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  45         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  46
  47 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  48         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  49
  50 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  51         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  52
  53 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  54         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  55
  56 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  58         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  59
  60 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  61         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  62         PAD_CTL_SRE_SLOW)
  63
  64 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  65         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  66         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  67
  68 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  69
  70 int dram_init(void)
  71 {
  72         gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
  73
  74         return 0;
  75 }
  76
  77 static iomux_v3_cfg_t const uart1_pads[] = {
  78         MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  79         MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  80 };
  81
  82 static iomux_v3_cfg_t const uart2_pads[] = {
  83         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  84         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  85 };
  86
  87 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  88
  89 /* I2C1, SGTL5000 */
  90 static struct i2c_pads_info i2c_pad_info0 = {
  91         .scl = {
  92                 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  93                 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
  94                 .gp = IMX_GPIO_NR(3, 21)
  95         },
  96         .sda = {
  97                 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  98                 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
  99                 .gp = IMX_GPIO_NR(3, 28)
 100         }
 101 };
 102
 103 /* I2C2 Camera, MIPI */
 104 static struct i2c_pads_info i2c_pad_info1 = {
 105         .scl = {
 106                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 107                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 108                 .gp = IMX_GPIO_NR(4, 12)
 109         },
 110         .sda = {
 111                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 112                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 113                 .gp = IMX_GPIO_NR(4, 13)
 114         }
 115 };
 116
 117 /* I2C3, J15 - RGB connector */
 118 static struct i2c_pads_info i2c_pad_info2 = {
 119         .scl = {
 120                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
 121                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
 122                 .gp = IMX_GPIO_NR(1, 5)
 123         },
 124         .sda = {
 125                 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
 126                 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
 127                 .gp = IMX_GPIO_NR(7, 11)
 128         }
 129 };
 130
 131 static iomux_v3_cfg_t const usdhc2_pads[] = {
 132         MX6_PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138 };
 139
 140 static iomux_v3_cfg_t const usdhc3_pads[] = {
 141         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 147         MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 148 };
 149
 150 static iomux_v3_cfg_t const usdhc4_pads[] = {
 151         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 152         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 153         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 154         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 155         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 156         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 157         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 158 };
 159
 160 static iomux_v3_cfg_t const enet_pads1[] = {
 161         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 162         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 163         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 165         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 167         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 168         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 169         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 170         /* pin 35 - 1 (PHY_AD2) on reset */
 171         MX6_PAD_RGMII_RXC__GPIO6_IO30           | MUX_PAD_CTRL(NO_PAD_CTRL),
 172         /* pin 32 - 1 - (MODE0) all */
 173         MX6_PAD_RGMII_RD0__GPIO6_IO25           | MUX_PAD_CTRL(NO_PAD_CTRL),
 174         /* pin 31 - 1 - (MODE1) all */
 175         MX6_PAD_RGMII_RD1__GPIO6_IO27           | MUX_PAD_CTRL(NO_PAD_CTRL),
 176         /* pin 28 - 1 - (MODE2) all */
 177         MX6_PAD_RGMII_RD2__GPIO6_IO28           | MUX_PAD_CTRL(NO_PAD_CTRL),
 178         /* pin 27 - 1 - (MODE3) all */
 179         MX6_PAD_RGMII_RD3__GPIO6_IO29           | MUX_PAD_CTRL(NO_PAD_CTRL),
 180         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 181         MX6_PAD_RGMII_RX_CTL__GPIO6_IO24        | MUX_PAD_CTRL(NO_PAD_CTRL),
 182         /* pin 42 PHY nRST */
 183         MX6_PAD_EIM_D23__GPIO3_IO23             | MUX_PAD_CTRL(NO_PAD_CTRL),
 184         MX6_PAD_ENET_RXD0__GPIO1_IO27           | MUX_PAD_CTRL(NO_PAD_CTRL),
 185 };
 186
 187 static iomux_v3_cfg_t const enet_pads2[] = {
 188         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 189         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 190         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 191         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 192         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 193         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 194 };
 195
 196 static iomux_v3_cfg_t const misc_pads[] = {
 197         MX6_PAD_GPIO_1__USB_OTG_ID              | MUX_PAD_CTRL(WEAK_PULLUP),
 198         MX6_PAD_KEY_COL4__USB_OTG_OC            | MUX_PAD_CTRL(WEAK_PULLUP),
 199         MX6_PAD_EIM_D30__USB_H1_OC              | MUX_PAD_CTRL(WEAK_PULLUP),
 200         /* OTG Power enable */
 201         MX6_PAD_EIM_D22__GPIO3_IO22             | MUX_PAD_CTRL(OUTPUT_40OHM),
 202 };
 203
 204 /* wl1271 pads on nitrogen6x */
 205 static iomux_v3_cfg_t const wl12xx_pads[] = {
 206         (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
 207                 | MUX_PAD_CTRL(WEAK_PULLDOWN),
 208         (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
 209                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 210         (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
 211                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 212 };
 213 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 214 #define WL12XX_WL_ENABLE_GP     IMX_GPIO_NR(6, 15)
 215 #define WL12XX_BT_ENABLE_GP     IMX_GPIO_NR(6, 16)
 216
 217 /* Button assignments for J14 */
 218 static iomux_v3_cfg_t const button_pads[] = {
 219         /* Menu */
 220         MX6_PAD_NANDF_D1__GPIO2_IO01    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 221         /* Back */
 222         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 223         /* Labelled Search (mapped to Power under Android) */
 224         MX6_PAD_NANDF_D3__GPIO2_IO03    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 225         /* Home */
 226         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 227         /* Volume Down */
 228         MX6_PAD_GPIO_19__GPIO4_IO05     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 229         /* Volume Up */
 230         MX6_PAD_GPIO_18__GPIO7_IO13     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 231 };
 232
 233 static void setup_iomux_enet(void)
 234 {
 235         gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
 236         gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
 237         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 238         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 239         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 240         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 241         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 242         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
 243         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 244
 245         /* Need delay 10ms according to KSZ9021 spec */
 246         udelay(1000 * 10);
 247         gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
 248         gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
 249
 250         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 251         udelay(100);    /* Wait 100 us before using mii interface */
 252 }
 253
 254 static iomux_v3_cfg_t const usb_pads[] = {
 255         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 256 };
 257
 258 static void setup_iomux_uart(void)
 259 {
 260         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 261         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 262 }
 263
 264 #ifdef CONFIG_USB_EHCI_MX6
 265 int board_ehci_hcd_init(int port)
 266 {
 267         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 268
 269         /* Reset USB hub */
 270         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 271         mdelay(2);
 272         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 273
 274         return 0;
 275 }
 276
 277 int board_ehci_power(int port, int on)
 278 {
 279         if (port)
 280                 return 0;
 281         gpio_set_value(GP_USB_OTG_PWR, on);
 282         return 0;
 283 }
 284
 285 #endif
 286
 287 #ifdef CONFIG_FSL_ESDHC_IMX
 288 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 289         {USDHC3_BASE_ADDR},
 290         {USDHC4_BASE_ADDR},
 291 };
 292
 293 int board_mmc_getcd(struct mmc *mmc)
 294 {
 295         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 296         int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
 297                         IMX_GPIO_NR(2, 6);
 298
 299         gpio_direction_input(gp_cd);
 300         return !gpio_get_value(gp_cd);
 301 }
 302
 303 int board_mmc_init(bd_t *bis)
 304 {
 305         int ret;
 306         u32 index = 0;
 307
 308         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 309         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 310
 311         usdhc_cfg[0].max_bus_width = 4;
 312         usdhc_cfg[1].max_bus_width = 4;
 313
 314         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 315                 switch (index) {
 316                 case 0:
 317                         imx_iomux_v3_setup_multiple_pads(
 318                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 319                         break;
 320                 case 1:
 321                        imx_iomux_v3_setup_multiple_pads(
 322                                usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 323                        break;
 324                 default:
 325                        printf("Warning: you configured more USDHC controllers"
 326                                "(%d) then supported by the board (%d)\n",
 327                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 328                        return -EINVAL;
 329                 }
 330
 331                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 332                 if (ret)
 333                         return ret;
 334         }
 335
 336         return 0;
 337 }
 338 #endif
 339
 340 #ifdef CONFIG_MXC_SPI
 341 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 342 {
 343         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 344 }
 345
 346 static iomux_v3_cfg_t const ecspi1_pads[] = {
 347         /* SS1 */
 348         MX6_PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(NO_PAD_CTRL),
 349         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 350         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 351         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 352 };
 353
 354 static void setup_spi(void)
 355 {
 356         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 357                                          ARRAY_SIZE(ecspi1_pads));
 358 }
 359 #endif
 360
 361 int board_phy_config(struct phy_device *phydev)
 362 {
 363         /* min rx data delay */
 364         ksz9021_phy_extended_write(phydev,
 365                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 366         /* min tx data delay */
 367         ksz9021_phy_extended_write(phydev,
 368                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 369         /* max rx/tx clock delay, min rx/tx control */
 370         ksz9021_phy_extended_write(phydev,
 371                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 372         if (phydev->drv->config)
 373                 phydev->drv->config(phydev);
 374
 375         return 0;
 376 }
 377
 378 int board_eth_init(bd_t *bis)
 379 {
 380         uint32_t base = IMX_FEC_BASE;
 381         struct mii_dev *bus = NULL;
 382         struct phy_device *phydev = NULL;
 383         int ret;
 384
 385         gpio_request(WL12XX_WL_IRQ_GP, "wifi_irq");
 386         gpio_request(IMX_GPIO_NR(6, 30), "rgmii_rxc");
 387         gpio_request(IMX_GPIO_NR(6, 25), "rgmii_rd0");
 388         gpio_request(IMX_GPIO_NR(6, 27), "rgmii_rd1");
 389         gpio_request(IMX_GPIO_NR(6, 28), "rgmii_rd2");
 390         gpio_request(IMX_GPIO_NR(6, 29), "rgmii_rd3");
 391         gpio_request(IMX_GPIO_NR(6, 24), "rgmii_rx_ctl");
 392         gpio_request(IMX_GPIO_NR(3, 23), "rgmii_reset_sabrelite");
 393         gpio_request(IMX_GPIO_NR(1, 27), "rgmii_reset_nitrogen6x");
 394         setup_iomux_enet();
 395
 396 #ifdef CONFIG_FEC_MXC
 397         bus = fec_get_miibus(base, -1);
 398         if (!bus)
 399                 return -EINVAL;
 400         /* scan phy 4,5,6,7 */
 401         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 402         if (!phydev) {
 403                 ret = -EINVAL;
 404                 goto free_bus;
 405         }
 406         printf("using phy at %d\n", phydev->addr);
 407         ret  = fec_probe(bis, -1, base, bus, phydev);
 408         if (ret)
 409                 goto free_phydev;
 410 #endif
 411
 412 #ifdef CONFIG_CI_UDC
 413         /* For otg ethernet*/
 414         usb_eth_initialize(bis);
 415 #endif
 416         return 0;
 417
 418 free_phydev:
 419         free(phydev);
 420 free_bus:
 421         free(bus);
 422         return ret;
 423 }
 424
 425 static void setup_buttons(void)
 426 {
 427         imx_iomux_v3_setup_multiple_pads(button_pads,
 428                                          ARRAY_SIZE(button_pads));
 429 }
 430
 431 #if defined(CONFIG_VIDEO_IPUV3)
 432
 433 static iomux_v3_cfg_t const backlight_pads[] = {
 434         /* Backlight on RGB connector: J15 */
 435         MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 436 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 437
 438         /* Backlight on LVDS connector: J6 */
 439         MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 440 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 441 };
 442
 443 static iomux_v3_cfg_t const rgb_pads[] = {
 444         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 445         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 446         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
 447         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
 448         MX6_PAD_DI0_PIN4__GPIO4_IO20,
 449         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 450         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 451         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 452         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 453         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 454         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 455         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 456         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 457         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 458         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 459         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 460         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 461         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 462         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 463         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 464         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 465         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 466         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 467         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 468         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 469         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 470         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 471         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 472         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 473 };
 474
 475 static void do_enable_hdmi(struct display_info_t const *dev)
 476 {
 477         imx_enable_hdmi_phy();
 478 }
 479
 480 static int detect_i2c(struct display_info_t const *dev)
 481 {
 482         return ((0 == i2c_set_bus_num(dev->bus))
 483                 &&
 484                 (0 == i2c_probe(dev->addr)));
 485 }
 486
 487 static void enable_lvds(struct display_info_t const *dev)
 488 {
 489         struct iomuxc *iomux = (struct iomuxc *)
 490                                 IOMUXC_BASE_ADDR;
 491         u32 reg = readl(&iomux->gpr[2]);
 492         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 493         writel(reg, &iomux->gpr[2]);
 494         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 495 }
 496
 497 static void enable_lvds_jeida(struct display_info_t const *dev)
 498 {
 499         struct iomuxc *iomux = (struct iomuxc *)
 500                                 IOMUXC_BASE_ADDR;
 501         u32 reg = readl(&iomux->gpr[2]);
 502         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 503              |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
 504         writel(reg, &iomux->gpr[2]);
 505         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 506 }
 507
 508 static void enable_rgb(struct display_info_t const *dev)
 509 {
 510         imx_iomux_v3_setup_multiple_pads(
 511                 rgb_pads,
 512                  ARRAY_SIZE(rgb_pads));
 513         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 514 }
 515
 516 struct display_info_t const displays[] = {{
 517         .bus    = 1,
 518         .addr   = 0x50,
 519         .pixfmt = IPU_PIX_FMT_RGB24,
 520         .detect = detect_i2c,
 521         .enable = do_enable_hdmi,
 522         .mode   = {
 523                 .name           = "HDMI",
 524                 .refresh        = 60,
 525                 .xres           = 1024,
 526                 .yres           = 768,
 527                 .pixclock       = 15385,
 528                 .left_margin    = 220,
 529                 .right_margin   = 40,
 530                 .upper_margin   = 21,
 531                 .lower_margin   = 7,
 532                 .hsync_len      = 60,
 533                 .vsync_len      = 10,
 534                 .sync           = FB_SYNC_EXT,
 535                 .vmode          = FB_VMODE_NONINTERLACED
 536 } }, {
 537         .bus    = 0,
 538         .addr   = 0,
 539         .pixfmt = IPU_PIX_FMT_RGB24,
 540         .detect = NULL,
 541         .enable = enable_lvds_jeida,
 542         .mode   = {
 543                 .name           = "LDB-WXGA",
 544                 .refresh        = 60,
 545                 .xres           = 1280,
 546                 .yres           = 800,
 547                 .pixclock       = 14065,
 548                 .left_margin    = 40,
 549                 .right_margin   = 40,
 550                 .upper_margin   = 3,
 551                 .lower_margin   = 80,
 552                 .hsync_len      = 10,
 553                 .vsync_len      = 10,
 554                 .sync           = FB_SYNC_EXT,
 555                 .vmode          = FB_VMODE_NONINTERLACED
 556 } }, {
 557         .bus    = 0,
 558         .addr   = 0,
 559         .pixfmt = IPU_PIX_FMT_RGB24,
 560         .detect = NULL,
 561         .enable = enable_lvds,
 562         .mode   = {
 563                 .name           = "LDB-WXGA-S",
 564                 .refresh        = 60,
 565                 .xres           = 1280,
 566                 .yres           = 800,
 567                 .pixclock       = 14065,
 568                 .left_margin    = 40,
 569                 .right_margin   = 40,
 570                 .upper_margin   = 3,
 571                 .lower_margin   = 80,
 572                 .hsync_len      = 10,
 573                 .vsync_len      = 10,
 574                 .sync           = FB_SYNC_EXT,
 575                 .vmode          = FB_VMODE_NONINTERLACED
 576 } }, {
 577         .bus    = 2,
 578         .addr   = 0x4,
 579         .pixfmt = IPU_PIX_FMT_LVDS666,
 580         .detect = detect_i2c,
 581         .enable = enable_lvds,
 582         .mode   = {
 583                 .name           = "Hannstar-XGA",
 584                 .refresh        = 60,
 585                 .xres           = 1024,
 586                 .yres           = 768,
 587                 .pixclock       = 15385,
 588                 .left_margin    = 220,
 589                 .right_margin   = 40,
 590                 .upper_margin   = 21,
 591                 .lower_margin   = 7,
 592                 .hsync_len      = 60,
 593                 .vsync_len      = 10,
 594                 .sync           = FB_SYNC_EXT,
 595                 .vmode          = FB_VMODE_NONINTERLACED
 596 } }, {
 597         .bus    = 0,
 598         .addr   = 0,
 599         .pixfmt = IPU_PIX_FMT_LVDS666,
 600         .detect = NULL,
 601         .enable = enable_lvds,
 602         .mode   = {
 603                 .name           = "LG-9.7",
 604                 .refresh        = 60,
 605                 .xres           = 1024,
 606                 .yres           = 768,
 607                 .pixclock       = 15385, /* ~65MHz */
 608                 .left_margin    = 480,
 609                 .right_margin   = 260,
 610                 .upper_margin   = 16,
 611                 .lower_margin   = 6,
 612                 .hsync_len      = 250,
 613                 .vsync_len      = 10,
 614                 .sync           = FB_SYNC_EXT,
 615                 .vmode          = FB_VMODE_NONINTERLACED
 616 } }, {
 617         .bus    = 2,
 618         .addr   = 0x38,
 619         .pixfmt = IPU_PIX_FMT_LVDS666,
 620         .detect = detect_i2c,
 621         .enable = enable_lvds,
 622         .mode   = {
 623                 .name           = "wsvga-lvds",
 624                 .refresh        = 60,
 625                 .xres           = 1024,
 626                 .yres           = 600,
 627                 .pixclock       = 15385,
 628                 .left_margin    = 220,
 629                 .right_margin   = 40,
 630                 .upper_margin   = 21,
 631                 .lower_margin   = 7,
 632                 .hsync_len      = 60,
 633                 .vsync_len      = 10,
 634                 .sync           = FB_SYNC_EXT,
 635                 .vmode          = FB_VMODE_NONINTERLACED
 636 } }, {
 637         .bus    = 2,
 638         .addr   = 0x10,
 639         .pixfmt = IPU_PIX_FMT_RGB666,
 640         .detect = detect_i2c,
 641         .enable = enable_rgb,
 642         .mode   = {
 643                 .name           = "fusion7",
 644                 .refresh        = 60,
 645                 .xres           = 800,
 646                 .yres           = 480,
 647                 .pixclock       = 33898,
 648                 .left_margin    = 96,
 649                 .right_margin   = 24,
 650                 .upper_margin   = 3,
 651                 .lower_margin   = 10,
 652                 .hsync_len      = 72,
 653                 .vsync_len      = 7,
 654                 .sync           = 0x40000002,
 655                 .vmode          = FB_VMODE_NONINTERLACED
 656 } }, {
 657         .bus    = 0,
 658         .addr   = 0,
 659         .pixfmt = IPU_PIX_FMT_RGB666,
 660         .detect = NULL,
 661         .enable = enable_rgb,
 662         .mode   = {
 663                 .name           = "svga",
 664                 .refresh        = 60,
 665                 .xres           = 800,
 666                 .yres           = 600,
 667                 .pixclock       = 15385,
 668                 .left_margin    = 220,
 669                 .right_margin   = 40,
 670                 .upper_margin   = 21,
 671                 .lower_margin   = 7,
 672                 .hsync_len      = 60,
 673                 .vsync_len      = 10,
 674                 .sync           = 0,
 675                 .vmode          = FB_VMODE_NONINTERLACED
 676 } }, {
 677         .bus    = 2,
 678         .addr   = 0x41,
 679         .pixfmt = IPU_PIX_FMT_LVDS666,
 680         .detect = detect_i2c,
 681         .enable = enable_lvds,
 682         .mode   = {
 683                 .name           = "amp1024x600",
 684                 .refresh        = 60,
 685                 .xres           = 1024,
 686                 .yres           = 600,
 687                 .pixclock       = 15385,
 688                 .left_margin    = 220,
 689                 .right_margin   = 40,
 690                 .upper_margin   = 21,
 691                 .lower_margin   = 7,
 692                 .hsync_len      = 60,
 693                 .vsync_len      = 10,
 694                 .sync           = FB_SYNC_EXT,
 695                 .vmode          = FB_VMODE_NONINTERLACED
 696 } }, {
 697         .bus    = 0,
 698         .addr   = 0,
 699         .pixfmt = IPU_PIX_FMT_LVDS666,
 700         .detect = 0,
 701         .enable = enable_lvds,
 702         .mode   = {
 703                 .name           = "wvga-lvds",
 704                 .refresh        = 57,
 705                 .xres           = 800,
 706                 .yres           = 480,
 707                 .pixclock       = 15385,
 708                 .left_margin    = 220,
 709                 .right_margin   = 40,
 710                 .upper_margin   = 21,
 711                 .lower_margin   = 7,
 712                 .hsync_len      = 60,
 713                 .vsync_len      = 10,
 714                 .sync           = FB_SYNC_EXT,
 715                 .vmode          = FB_VMODE_NONINTERLACED
 716 } }, {
 717         .bus    = 2,
 718         .addr   = 0x48,
 719         .pixfmt = IPU_PIX_FMT_RGB666,
 720         .detect = detect_i2c,
 721         .enable = enable_rgb,
 722         .mode   = {
 723                 .name           = "wvga-rgb",
 724                 .refresh        = 57,
 725                 .xres           = 800,
 726                 .yres           = 480,
 727                 .pixclock       = 37037,
 728                 .left_margin    = 40,
 729                 .right_margin   = 60,
 730                 .upper_margin   = 10,
 731                 .lower_margin   = 10,
 732                 .hsync_len      = 20,
 733                 .vsync_len      = 10,
 734                 .sync           = 0,
 735                 .vmode          = FB_VMODE_NONINTERLACED
 736 } }, {
 737         .bus    = 0,
 738         .addr   = 0,
 739         .pixfmt = IPU_PIX_FMT_RGB24,
 740         .detect = NULL,
 741         .enable = enable_rgb,
 742         .mode   = {
 743                 .name           = "qvga",
 744                 .refresh        = 60,
 745                 .xres           = 320,
 746                 .yres           = 240,
 747                 .pixclock       = 37037,
 748                 .left_margin    = 38,
 749                 .right_margin   = 37,
 750                 .upper_margin   = 16,
 751                 .lower_margin   = 15,
 752                 .hsync_len      = 30,
 753                 .vsync_len      = 3,
 754                 .sync           = 0,
 755                 .vmode          = FB_VMODE_NONINTERLACED
 756 } } };
 757 size_t display_count = ARRAY_SIZE(displays);
 758
 759 int board_cfb_skip(void)
 760 {
 761         return NULL != env_get("novideo");
 762 }
 763
 764 static void setup_display(void)
 765 {
 766         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 767         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 768         int reg;
 769
 770         enable_ipu_clock();
 771         imx_setup_hdmi();
 772         /* Turn on LDB0,IPU,IPU DI0 clocks */
 773         reg = __raw_readl(&mxc_ccm->CCGR3);
 774         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
 775         writel(reg, &mxc_ccm->CCGR3);
 776
 777         /* set LDB0, LDB1 clk select to 011/011 */
 778         reg = readl(&mxc_ccm->cs2cdr);
 779         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 780                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 781         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 782               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 783         writel(reg, &mxc_ccm->cs2cdr);
 784
 785         reg = readl(&mxc_ccm->cscmr2);
 786         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 787         writel(reg, &mxc_ccm->cscmr2);
 788
 789         reg = readl(&mxc_ccm->chsccdr);
 790         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 791                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 792         writel(reg, &mxc_ccm->chsccdr);
 793
 794         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 795              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 796              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 797              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 798              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 799              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 800              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 801              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 802              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 803         writel(reg, &iomux->gpr[2]);
 804
 805         reg = readl(&iomux->gpr[3]);
 806         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 807                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 808             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 809                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 810         writel(reg, &iomux->gpr[3]);
 811
 812         /* backlights off until needed */
 813         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 814                                          ARRAY_SIZE(backlight_pads));
 815         gpio_direction_input(LVDS_BACKLIGHT_GP);
 816         gpio_direction_input(RGB_BACKLIGHT_GP);
 817 }
 818 #endif
 819
 820 static iomux_v3_cfg_t const init_pads[] = {
 821         /* SGTL5000 sys_mclk */
 822         NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
 823
 824         /* J5 - Camera MCLK */
 825         NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
 826
 827         /* wl1271 pads on nitrogen6x */
 828         /* WL12XX_WL_IRQ_GP */
 829         NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 830         /* WL12XX_WL_ENABLE_GP */
 831         NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 832         /* WL12XX_BT_ENABLE_GP */
 833         NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 834         /* USB otg power */
 835         NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 836         NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
 837         NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
 838         NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
 839         NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
 840 };
 841
 842 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 843
 844 static unsigned gpios_out_low[] = {
 845         /* Disable wl1271 */
 846         IMX_GPIO_NR(6, 15),     /* disable wireless */
 847         IMX_GPIO_NR(6, 16),     /* disable bluetooth */
 848         IMX_GPIO_NR(3, 22),     /* disable USB otg power */
 849         IMX_GPIO_NR(2, 5),      /* ov5640 mipi camera reset */
 850         IMX_GPIO_NR(1, 8),      /* ov5642 reset */
 851 };
 852
 853 static unsigned gpios_out_high[] = {
 854         IMX_GPIO_NR(1, 6),      /* ov5642 powerdown */
 855         IMX_GPIO_NR(6, 9),      /* ov5640 mipi camera power down */
 856 };
 857
 858 static void set_gpios(unsigned *p, int cnt, int val)
 859 {
 860         int i;
 861
 862         for (i = 0; i < cnt; i++)
 863                 gpio_direction_output(*p++, val);
 864 }
 865
 866 int board_early_init_f(void)
 867 {
 868         setup_iomux_uart();
 869
 870         set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
 871         set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
 872         gpio_direction_input(WL12XX_WL_IRQ_GP);
 873
 874         imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
 875         imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
 876         setup_buttons();
 877
 878 #if defined(CONFIG_VIDEO_IPUV3)
 879         setup_display();
 880 #endif
 881         return 0;
 882 }
 883
 884 /*
 885  * Do not overwrite the console
 886  * Use always serial for U-Boot console
 887  */
 888 int overwrite_console(void)
 889 {
 890         return 1;
 891 }
 892
 893 int board_init(void)
 894 {
 895         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 896
 897         clrsetbits_le32(&iomuxc_regs->gpr[1],
 898                         IOMUXC_GPR1_OTG_ID_MASK,
 899                         IOMUXC_GPR1_OTG_ID_GPIO1);
 900
 901         imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
 902
 903         /* address of boot parameters */
 904         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 905
 906 #ifdef CONFIG_MXC_SPI
 907         setup_spi();
 908 #endif
 909         imx_iomux_v3_setup_multiple_pads(
 910                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 911         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 912         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 913         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 914
 915 #ifdef CONFIG_SATA
 916         setup_sata();
 917 #endif
 918
 919         return 0;
 920 }
 921
 922 int checkboard(void)
 923 {
 924         int ret = gpio_get_value(WL12XX_WL_IRQ_GP);
 925
 926         if (ret < 0) {
 927                 /* The gpios have not been probed yet. Read it myself */
 928                 struct gpio_regs *regs = (struct gpio_regs *)GPIO6_BASE_ADDR;
 929                 int gpio = WL12XX_WL_IRQ_GP & 0x1f;
 930
 931                 ret = (readl(&regs->gpio_psr) >> gpio) & 0x01;
 932         }
 933         if (ret)
 934                 puts("Board: Nitrogen6X\n");
 935         else
 936                 puts("Board: SABRE Lite\n");
 937
 938         return 0;
 939 }
 940
 941 struct button_key {
 942         char const      *name;
 943         unsigned        gpnum;
 944         char            ident;
 945 };
 946
 947 static struct button_key const buttons[] = {
 948         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 949         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 950         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 951         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 952         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 953         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 954 };
 955
 956 /*
 957  * generate a null-terminated string containing the buttons pressed
 958  * returns number of keys pressed
 959  */
 960 static int read_keys(char *buf)
 961 {
 962         int i, numpressed = 0;
 963         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 964                 if (!gpio_get_value(buttons[i].gpnum))
 965                         buf[numpressed++] = buttons[i].ident;
 966         }
 967         buf[numpressed] = '\0';
 968         return numpressed;
 969 }
 970
 971 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 972 {
 973         char envvalue[ARRAY_SIZE(buttons)+1];
 974         int numpressed = read_keys(envvalue);
 975         env_set("keybd", envvalue);
 976         return numpressed == 0;
 977 }
 978
 979 U_BOOT_CMD(
 980         kbd, 1, 1, do_kbd,
 981         "Tests for keypresses, sets 'keybd' environment variable",
 982         "Returns 0 (true) to shell if key is pressed."
 983 );
 984
 985 #ifdef CONFIG_PREBOOT
 986 static char const kbd_magic_prefix[] = "key_magic";
 987 static char const kbd_command_prefix[] = "key_cmd";
 988
 989 static void preboot_keys(void)
 990 {
 991         int numpressed;
 992         char keypress[ARRAY_SIZE(buttons)+1];
 993         numpressed = read_keys(keypress);
 994         if (numpressed) {
 995                 char *kbd_magic_keys = env_get("magic_keys");
 996                 char *suffix;
 997                 /*
 998                  * loop over all magic keys
 999                  */
1000                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
1001                         char *keys;
1002                         char magic[sizeof(kbd_magic_prefix) + 1];
1003                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
1004                         keys = env_get(magic);
1005                         if (keys) {
1006                                 if (!strcmp(keys, keypress))
1007                                         break;
1008                         }
1009                 }
1010                 if (*suffix) {
1011                         char cmd_name[sizeof(kbd_command_prefix) + 1];
1012                         char *cmd;
1013                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
1014                         cmd = env_get(cmd_name);
1015                         if (cmd) {
1016                                 env_set("preboot", cmd);
1017                                 return;
1018                         }
1019                 }
1020         }
1021 }
1022 #endif
1023
1024 #ifdef CONFIG_CMD_BMODE
1025 static const struct boot_mode board_boot_modes[] = {
1026         /* 4 bit bus width */
1027         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
1028         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
1029         {NULL,          0},
1030 };
1031 #endif
1032
1033 int misc_init_r(void)
1034 {
1035         gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
1036         gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
1037         gpio_request(GP_USB_OTG_PWR, "usbotg power");
1038         gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset");
1039         gpio_request(IMX_GPIO_NR(2, 2), "back");
1040         gpio_request(IMX_GPIO_NR(2, 4), "home");
1041         gpio_request(IMX_GPIO_NR(2, 1), "menu");
1042         gpio_request(IMX_GPIO_NR(2, 3), "search");
1043         gpio_request(IMX_GPIO_NR(7, 13), "volup");
1044         gpio_request(IMX_GPIO_NR(4, 5), "voldown");
1045 #ifdef CONFIG_PREBOOT
1046         preboot_keys();
1047 #endif
1048
1049 #ifdef CONFIG_CMD_BMODE
1050         add_board_boot_modes(board_boot_modes);
1051 #endif
1052         env_set_hex("reset_cause", get_imx_reset_cause());
1053         return 0;
1054 }