board/boundary/nitrogen6x/nitrogen6x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <env.h>
  10 #include <init.h>
  11 #include <net.h>
  12 #include <asm/global_data.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/iomux.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <malloc.h>
  19 #include <asm/arch/mx6-pins.h>
  20 #include <linux/delay.h>
  21 #include <linux/errno.h>
  22 #include <asm/gpio.h>
  23 #include <asm/mach-imx/iomux-v3.h>
  24 #include <asm/mach-imx/mxc_i2c.h>
  25 #include <asm/mach-imx/sata.h>
  26 #include <asm/mach-imx/spi.h>
  27 #include <asm/mach-imx/boot_mode.h>
  28 #include <asm/mach-imx/video.h>
  29 #include <fsl_esdhc_imx.h>
  30 #include <micrel.h>
  31 #include <miiphy.h>
  32 #include <netdev.h>
  33 #include <asm/arch/crm_regs.h>
  34 #include <asm/arch/mxc_hdmi.h>
  35 #include <i2c.h>
  36 #include <input.h>
  37 #include <netdev.h>
  38 #include <usb/ehci-ci.h>
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  42
  43 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  44         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  45         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  46
  47 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  48         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  49         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  50
  51 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  52         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  53
  54 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  55         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  56
  57 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  58         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  59
  60 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  61         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  62         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  63
  64 #define RGB_PAD_CTRL    PAD_CTL_DSE_120ohm
  65
  66 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  67         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  68         PAD_CTL_SRE_SLOW)
  69
  70 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  71         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  72         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  73
  74 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  75
  76 /* Prevent compiler error if gpio number 08 or 09 is used */
  77 #define not_octal(gp) ((((0x##gp >> 4) & 0xf) * 10) + ((0x##gp & 0xf)))
  78
  79 #define _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,             \
  80                 sda_pad, sda_bank, sda_gp, pad_ctrl, join_io) {                \
  81         .scl = {                                                               \
  82                 .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##scl_pad##__##i2cnum##_SCL,\
  83                                          pad_ctrl),                            \
  84                 .gpio_mode = NEW_PAD_CTRL(                                     \
  85                         cpu##_PAD_##scl_pad##__GPIO##scl_bank##join_io##scl_gp,\
  86                         pad_ctrl),                                             \
  87                 .gp = IMX_GPIO_NR(scl_bank, not_octal(scl_gp))                 \
  88         },                                                                     \
  89         .sda = {                                                               \
  90                 .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##sda_pad##__##i2cnum##_SDA,\
  91                                          pad_ctrl),                            \
  92                 .gpio_mode = NEW_PAD_CTRL(                                     \
  93                         cpu##_PAD_##sda_pad##__GPIO##sda_bank##join_io##sda_gp,\
  94                         pad_ctrl),                                             \
  95                         .gp = IMX_GPIO_NR(sda_bank, not_octal(sda_gp))         \
  96         }                                                                      \
  97 }
  98
  99 #define I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,              \
 100                 sda_pad, sda_bank, sda_gp, pad_ctrl)                           \
 101                 _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,     \
 102                                 sda_pad, sda_bank, sda_gp, pad_ctrl, _IO)
 103
 104 #if defined(CONFIG_MX6QDL)
 105 #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp,          \
 106                 sda_pad, sda_bank, sda_gp, pad_ctrl)                    \
 107         I2C_PADS_INFO_CPU(MX6Q, i2cnum, scl_pad, scl_bank, scl_gp,      \
 108                 sda_pad, sda_bank, sda_gp, pad_ctrl),                   \
 109         I2C_PADS_INFO_CPU(MX6DL, i2cnum, scl_pad, scl_bank, scl_gp,     \
 110                 sda_pad, sda_bank, sda_gp, pad_ctrl)
 111 #define I2C_PADS_INFO_ENTRY_SPACING 2
 112
 113 #define IOMUX_PAD_CTRL(name, pad_ctrl) \
 114                 NEW_PAD_CTRL(MX6Q_PAD_##name, pad_ctrl),        \
 115                 NEW_PAD_CTRL(MX6DL_PAD_##name, pad_ctrl)
 116 #else
 117 #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp,          \
 118                 sda_pad, sda_bank, sda_gp, pad_ctrl)                    \
 119         I2C_PADS_INFO_CPU(MX6, i2cnum, scl_pad, scl_bank, scl_gp,       \
 120                 sda_pad, sda_bank, sda_gp, pad_ctrl)
 121 #define I2C_PADS_INFO_ENTRY_SPACING 1
 122
 123 #define IOMUX_PAD_CTRL(name, pad_ctrl) NEW_PAD_CTRL(MX6_PAD_##name, pad_ctrl)
 124 #endif
 125
 126 int dram_init(void)
 127 {
 128         gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
 129
 130         return 0;
 131 }
 132
 133 static iomux_v3_cfg_t const uart1_pads[] = {
 134         IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
 135         IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
 136 };
 137
 138 static iomux_v3_cfg_t const uart2_pads[] = {
 139         IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
 140         IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
 141 };
 142
 143 static struct i2c_pads_info i2c_pads[] = {
 144         /* I2C1, SGTL5000 */
 145         I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
 146         /* I2C2 Camera, MIPI */
 147         I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13,
 148                             I2C_PAD_CTRL),
 149         /* I2C3, J15 - RGB connector */
 150         I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
 151 };
 152
 153 #define I2C_BUS_CNT    3
 154
 155 static iomux_v3_cfg_t const usdhc2_pads[] = {
 156         IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
 157         IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
 158         IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
 159         IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
 160         IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
 161         IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
 162 };
 163
 164 static iomux_v3_cfg_t const enet_pads1[] = {
 165         IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
 166         IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
 167         IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL),
 168         IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
 169         IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
 170         IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
 171         IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
 172         IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
 173         IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL),
 174         /* pin 35 - 1 (PHY_AD2) on reset */
 175         IOMUX_PAD_CTRL(RGMII_RXC__GPIO6_IO30, NO_PAD_CTRL),
 176         /* pin 32 - 1 - (MODE0) all */
 177         IOMUX_PAD_CTRL(RGMII_RD0__GPIO6_IO25, NO_PAD_CTRL),
 178         /* pin 31 - 1 - (MODE1) all */
 179         IOMUX_PAD_CTRL(RGMII_RD1__GPIO6_IO27, NO_PAD_CTRL),
 180         /* pin 28 - 1 - (MODE2) all */
 181         IOMUX_PAD_CTRL(RGMII_RD2__GPIO6_IO28, NO_PAD_CTRL),
 182         /* pin 27 - 1 - (MODE3) all */
 183         IOMUX_PAD_CTRL(RGMII_RD3__GPIO6_IO29, NO_PAD_CTRL),
 184         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 185         IOMUX_PAD_CTRL(RGMII_RX_CTL__GPIO6_IO24, NO_PAD_CTRL),
 186         /* pin 42 PHY nRST */
 187         IOMUX_PAD_CTRL(EIM_D23__GPIO3_IO23, NO_PAD_CTRL),
 188         IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, NO_PAD_CTRL),
 189 };
 190
 191 static iomux_v3_cfg_t const enet_pads2[] = {
 192         IOMUX_PAD_CTRL(RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL),
 193         IOMUX_PAD_CTRL(RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL),
 194         IOMUX_PAD_CTRL(RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL),
 195         IOMUX_PAD_CTRL(RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL),
 196         IOMUX_PAD_CTRL(RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL),
 197         IOMUX_PAD_CTRL(RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL),
 198 };
 199
 200 static iomux_v3_cfg_t const misc_pads[] = {
 201         IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
 202         IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
 203         IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
 204         /* OTG Power enable */
 205         IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 206 };
 207
 208 /* wl1271 pads on nitrogen6x */
 209 static iomux_v3_cfg_t const wl12xx_pads[] = {
 210         IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 211         IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 212         IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 213 };
 214 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 215 #define WL12XX_WL_ENABLE_GP     IMX_GPIO_NR(6, 15)
 216 #define WL12XX_BT_ENABLE_GP     IMX_GPIO_NR(6, 16)
 217
 218 /* Button assignments for J14 */
 219 static iomux_v3_cfg_t const button_pads[] = {
 220         /* Menu */
 221         IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, BUTTON_PAD_CTRL),
 222         /* Back */
 223         IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, BUTTON_PAD_CTRL),
 224         /* Labelled Search (mapped to Power under Android) */
 225         IOMUX_PAD_CTRL(NANDF_D3__GPIO2_IO03, BUTTON_PAD_CTRL),
 226         /* Home */
 227         IOMUX_PAD_CTRL(NANDF_D4__GPIO2_IO04, BUTTON_PAD_CTRL),
 228         /* Volume Down */
 229         IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, BUTTON_PAD_CTRL),
 230         /* Volume Up */
 231         IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, BUTTON_PAD_CTRL),
 232 };
 233
 234 static void setup_iomux_enet(void)
 235 {
 236         gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
 237         gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
 238         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 239         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 240         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 241         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 242         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 243         SETUP_IOMUX_PADS(enet_pads1);
 244         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 245
 246         /* Need delay 10ms according to KSZ9021 spec */
 247         udelay(1000 * 10);
 248         gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
 249         gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
 250
 251         SETUP_IOMUX_PADS(enet_pads2);
 252         udelay(100);    /* Wait 100 us before using mii interface */
 253 }
 254
 255 static iomux_v3_cfg_t const usb_pads[] = {
 256         IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, NO_PAD_CTRL),
 257 };
 258
 259 static void setup_iomux_uart(void)
 260 {
 261         SETUP_IOMUX_PADS(uart1_pads);
 262         SETUP_IOMUX_PADS(uart2_pads);
 263 }
 264
 265 #ifdef CONFIG_USB_EHCI_MX6
 266 int board_ehci_hcd_init(int port)
 267 {
 268         SETUP_IOMUX_PADS(usb_pads);
 269
 270         /* Reset USB hub */
 271         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 272         mdelay(2);
 273         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 274
 275         return 0;
 276 }
 277
 278 int board_ehci_power(int port, int on)
 279 {
 280         if (port)
 281                 return 0;
 282         gpio_set_value(GP_USB_OTG_PWR, on);
 283         return 0;
 284 }
 285
 286 #endif
 287
 288 #ifdef CONFIG_MXC_SPI
 289 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 290 {
 291         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 292 }
 293
 294 static iomux_v3_cfg_t const ecspi1_pads[] = {
 295         /* SS1 */
 296         IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, NO_PAD_CTRL),
 297         IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
 298         IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
 299         IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
 300 };
 301
 302 static void setup_spi(void)
 303 {
 304         SETUP_IOMUX_PADS(ecspi1_pads);
 305 }
 306 #endif
 307
 308 int board_phy_config(struct phy_device *phydev)
 309 {
 310         /* min rx data delay */
 311         ksz9021_phy_extended_write(phydev,
 312                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 313         /* min tx data delay */
 314         ksz9021_phy_extended_write(phydev,
 315                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 316         /* max rx/tx clock delay, min rx/tx control */
 317         ksz9021_phy_extended_write(phydev,
 318                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 319         if (phydev->drv->config)
 320                 phydev->drv->config(phydev);
 321
 322         return 0;
 323 }
 324
 325 int board_eth_init(struct bd_info *bis)
 326 {
 327         uint32_t base = IMX_FEC_BASE;
 328         struct mii_dev *bus = NULL;
 329         struct phy_device *phydev = NULL;
 330         int ret;
 331
 332         gpio_request(WL12XX_WL_IRQ_GP, "wifi_irq");
 333         gpio_request(IMX_GPIO_NR(6, 30), "rgmii_rxc");
 334         gpio_request(IMX_GPIO_NR(6, 25), "rgmii_rd0");
 335         gpio_request(IMX_GPIO_NR(6, 27), "rgmii_rd1");
 336         gpio_request(IMX_GPIO_NR(6, 28), "rgmii_rd2");
 337         gpio_request(IMX_GPIO_NR(6, 29), "rgmii_rd3");
 338         gpio_request(IMX_GPIO_NR(6, 24), "rgmii_rx_ctl");
 339         gpio_request(IMX_GPIO_NR(3, 23), "rgmii_reset_sabrelite");
 340         gpio_request(IMX_GPIO_NR(1, 27), "rgmii_reset_nitrogen6x");
 341         setup_iomux_enet();
 342
 343 #ifdef CONFIG_FEC_MXC
 344         bus = fec_get_miibus(base, -1);
 345         if (!bus)
 346                 return -EINVAL;
 347         /* scan phy 4,5,6,7 */
 348         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 349         if (!phydev) {
 350                 ret = -EINVAL;
 351                 goto free_bus;
 352         }
 353         printf("using phy at %d\n", phydev->addr);
 354         ret  = fec_probe(bis, -1, base, bus, phydev);
 355         if (ret)
 356                 goto free_phydev;
 357 #endif
 358
 359 #ifdef CONFIG_CI_UDC
 360         /* For otg ethernet*/
 361         usb_eth_initialize(bis);
 362 #endif
 363         return 0;
 364
 365 free_phydev:
 366         free(phydev);
 367 free_bus:
 368         free(bus);
 369         return ret;
 370 }
 371
 372 static void setup_buttons(void)
 373 {
 374         SETUP_IOMUX_PADS(button_pads);
 375 }
 376
 377 #if defined(CONFIG_VIDEO_IPUV3)
 378
 379 static iomux_v3_cfg_t const backlight_pads[] = {
 380         /* Backlight on RGB connector: J15 */
 381         IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, NO_PAD_CTRL),
 382 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 383
 384         /* Backlight on LVDS connector: J6 */
 385         IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, NO_PAD_CTRL),
 386 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 387 };
 388
 389 static iomux_v3_cfg_t const rgb_pads[] = {
 390         IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
 391         IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL),
 392         IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL),
 393         IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL),
 394         IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, RGB_PAD_CTRL),
 395         IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
 396         IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
 397         IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
 398         IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
 399         IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
 400         IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL),
 401         IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL),
 402         IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL),
 403         IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL),
 404         IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL),
 405         IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL),
 406         IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL),
 407         IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL),
 408         IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL),
 409         IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL),
 410         IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL),
 411         IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL),
 412         IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL),
 413         IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL),
 414         IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL),
 415         IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL),
 416         IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL),
 417         IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL),
 418         IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL),
 419 };
 420
 421 static void do_enable_hdmi(struct display_info_t const *dev)
 422 {
 423         imx_enable_hdmi_phy();
 424 }
 425
 426 static int detect_i2c(struct display_info_t const *dev)
 427 {
 428         return ((0 == i2c_set_bus_num(dev->bus))
 429                 &&
 430                 (0 == i2c_probe(dev->addr)));
 431 }
 432
 433 static void enable_lvds(struct display_info_t const *dev)
 434 {
 435         struct iomuxc *iomux = (struct iomuxc *)
 436                                 IOMUXC_BASE_ADDR;
 437         u32 reg = readl(&iomux->gpr[2]);
 438         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 439         writel(reg, &iomux->gpr[2]);
 440         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 441 }
 442
 443 static void enable_lvds_jeida(struct display_info_t const *dev)
 444 {
 445         struct iomuxc *iomux = (struct iomuxc *)
 446                                 IOMUXC_BASE_ADDR;
 447         u32 reg = readl(&iomux->gpr[2]);
 448         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 449              |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
 450         writel(reg, &iomux->gpr[2]);
 451         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 452 }
 453
 454 static void enable_rgb(struct display_info_t const *dev)
 455 {
 456         SETUP_IOMUX_PADS(rgb_pads);
 457         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 458 }
 459
 460 struct display_info_t const displays[] = {{
 461         .bus    = 1,
 462         .addr   = 0x50,
 463         .pixfmt = IPU_PIX_FMT_RGB24,
 464         .detect = detect_i2c,
 465         .enable = do_enable_hdmi,
 466         .mode   = {
 467                 .name           = "HDMI",
 468                 .refresh        = 60,
 469                 .xres           = 1024,
 470                 .yres           = 768,
 471                 .pixclock       = 15385,
 472                 .left_margin    = 220,
 473                 .right_margin   = 40,
 474                 .upper_margin   = 21,
 475                 .lower_margin   = 7,
 476                 .hsync_len      = 60,
 477                 .vsync_len      = 10,
 478                 .sync           = FB_SYNC_EXT,
 479                 .vmode          = FB_VMODE_NONINTERLACED
 480 } }, {
 481         .bus    = 0,
 482         .addr   = 0,
 483         .pixfmt = IPU_PIX_FMT_RGB24,
 484         .detect = NULL,
 485         .enable = enable_lvds_jeida,
 486         .mode   = {
 487                 .name           = "LDB-WXGA",
 488                 .refresh        = 60,
 489                 .xres           = 1280,
 490                 .yres           = 800,
 491                 .pixclock       = 14065,
 492                 .left_margin    = 40,
 493                 .right_margin   = 40,
 494                 .upper_margin   = 3,
 495                 .lower_margin   = 80,
 496                 .hsync_len      = 10,
 497                 .vsync_len      = 10,
 498                 .sync           = FB_SYNC_EXT,
 499                 .vmode          = FB_VMODE_NONINTERLACED
 500 } }, {
 501         .bus    = 0,
 502         .addr   = 0,
 503         .pixfmt = IPU_PIX_FMT_RGB24,
 504         .detect = NULL,
 505         .enable = enable_lvds,
 506         .mode   = {
 507                 .name           = "LDB-WXGA-S",
 508                 .refresh        = 60,
 509                 .xres           = 1280,
 510                 .yres           = 800,
 511                 .pixclock       = 14065,
 512                 .left_margin    = 40,
 513                 .right_margin   = 40,
 514                 .upper_margin   = 3,
 515                 .lower_margin   = 80,
 516                 .hsync_len      = 10,
 517                 .vsync_len      = 10,
 518                 .sync           = FB_SYNC_EXT,
 519                 .vmode          = FB_VMODE_NONINTERLACED
 520 } }, {
 521         .bus    = 2,
 522         .addr   = 0x4,
 523         .pixfmt = IPU_PIX_FMT_LVDS666,
 524         .detect = detect_i2c,
 525         .enable = enable_lvds,
 526         .mode   = {
 527                 .name           = "Hannstar-XGA",
 528                 .refresh        = 60,
 529                 .xres           = 1024,
 530                 .yres           = 768,
 531                 .pixclock       = 15385,
 532                 .left_margin    = 220,
 533                 .right_margin   = 40,
 534                 .upper_margin   = 21,
 535                 .lower_margin   = 7,
 536                 .hsync_len      = 60,
 537                 .vsync_len      = 10,
 538                 .sync           = FB_SYNC_EXT,
 539                 .vmode          = FB_VMODE_NONINTERLACED
 540 } }, {
 541         .bus    = 0,
 542         .addr   = 0,
 543         .pixfmt = IPU_PIX_FMT_LVDS666,
 544         .detect = NULL,
 545         .enable = enable_lvds,
 546         .mode   = {
 547                 .name           = "LG-9.7",
 548                 .refresh        = 60,
 549                 .xres           = 1024,
 550                 .yres           = 768,
 551                 .pixclock       = 15385, /* ~65MHz */
 552                 .left_margin    = 480,
 553                 .right_margin   = 260,
 554                 .upper_margin   = 16,
 555                 .lower_margin   = 6,
 556                 .hsync_len      = 250,
 557                 .vsync_len      = 10,
 558                 .sync           = FB_SYNC_EXT,
 559                 .vmode          = FB_VMODE_NONINTERLACED
 560 } }, {
 561         .bus    = 2,
 562         .addr   = 0x38,
 563         .pixfmt = IPU_PIX_FMT_LVDS666,
 564         .detect = detect_i2c,
 565         .enable = enable_lvds,
 566         .mode   = {
 567                 .name           = "wsvga-lvds",
 568                 .refresh        = 60,
 569                 .xres           = 1024,
 570                 .yres           = 600,
 571                 .pixclock       = 15385,
 572                 .left_margin    = 220,
 573                 .right_margin   = 40,
 574                 .upper_margin   = 21,
 575                 .lower_margin   = 7,
 576                 .hsync_len      = 60,
 577                 .vsync_len      = 10,
 578                 .sync           = FB_SYNC_EXT,
 579                 .vmode          = FB_VMODE_NONINTERLACED
 580 } }, {
 581         .bus    = 2,
 582         .addr   = 0x10,
 583         .pixfmt = IPU_PIX_FMT_RGB666,
 584         .detect = detect_i2c,
 585         .enable = enable_rgb,
 586         .mode   = {
 587                 .name           = "fusion7",
 588                 .refresh        = 60,
 589                 .xres           = 800,
 590                 .yres           = 480,
 591                 .pixclock       = 33898,
 592                 .left_margin    = 96,
 593                 .right_margin   = 24,
 594                 .upper_margin   = 3,
 595                 .lower_margin   = 10,
 596                 .hsync_len      = 72,
 597                 .vsync_len      = 7,
 598                 .sync           = 0x40000002,
 599                 .vmode          = FB_VMODE_NONINTERLACED
 600 } }, {
 601         .bus    = 0,
 602         .addr   = 0,
 603         .pixfmt = IPU_PIX_FMT_RGB666,
 604         .detect = NULL,
 605         .enable = enable_rgb,
 606         .mode   = {
 607                 .name           = "svga",
 608                 .refresh        = 60,
 609                 .xres           = 800,
 610                 .yres           = 600,
 611                 .pixclock       = 15385,
 612                 .left_margin    = 220,
 613                 .right_margin   = 40,
 614                 .upper_margin   = 21,
 615                 .lower_margin   = 7,
 616                 .hsync_len      = 60,
 617                 .vsync_len      = 10,
 618                 .sync           = 0,
 619                 .vmode          = FB_VMODE_NONINTERLACED
 620 } }, {
 621         .bus    = 2,
 622         .addr   = 0x41,
 623         .pixfmt = IPU_PIX_FMT_LVDS666,
 624         .detect = detect_i2c,
 625         .enable = enable_lvds,
 626         .mode   = {
 627                 .name           = "amp1024x600",
 628                 .refresh        = 60,
 629                 .xres           = 1024,
 630                 .yres           = 600,
 631                 .pixclock       = 15385,
 632                 .left_margin    = 220,
 633                 .right_margin   = 40,
 634                 .upper_margin   = 21,
 635                 .lower_margin   = 7,
 636                 .hsync_len      = 60,
 637                 .vsync_len      = 10,
 638                 .sync           = FB_SYNC_EXT,
 639                 .vmode          = FB_VMODE_NONINTERLACED
 640 } }, {
 641         .bus    = 0,
 642         .addr   = 0,
 643         .pixfmt = IPU_PIX_FMT_LVDS666,
 644         .detect = 0,
 645         .enable = enable_lvds,
 646         .mode   = {
 647                 .name           = "wvga-lvds",
 648                 .refresh        = 57,
 649                 .xres           = 800,
 650                 .yres           = 480,
 651                 .pixclock       = 15385,
 652                 .left_margin    = 220,
 653                 .right_margin   = 40,
 654                 .upper_margin   = 21,
 655                 .lower_margin   = 7,
 656                 .hsync_len      = 60,
 657                 .vsync_len      = 10,
 658                 .sync           = FB_SYNC_EXT,
 659                 .vmode          = FB_VMODE_NONINTERLACED
 660 } }, {
 661         .bus    = 2,
 662         .addr   = 0x48,
 663         .pixfmt = IPU_PIX_FMT_RGB666,
 664         .detect = detect_i2c,
 665         .enable = enable_rgb,
 666         .mode   = {
 667                 .name           = "wvga-rgb",
 668                 .refresh        = 57,
 669                 .xres           = 800,
 670                 .yres           = 480,
 671                 .pixclock       = 37037,
 672                 .left_margin    = 40,
 673                 .right_margin   = 60,
 674                 .upper_margin   = 10,
 675                 .lower_margin   = 10,
 676                 .hsync_len      = 20,
 677                 .vsync_len      = 10,
 678                 .sync           = 0,
 679                 .vmode          = FB_VMODE_NONINTERLACED
 680 } }, {
 681         .bus    = 0,
 682         .addr   = 0,
 683         .pixfmt = IPU_PIX_FMT_RGB24,
 684         .detect = NULL,
 685         .enable = enable_rgb,
 686         .mode   = {
 687                 .name           = "qvga",
 688                 .refresh        = 60,
 689                 .xres           = 320,
 690                 .yres           = 240,
 691                 .pixclock       = 37037,
 692                 .left_margin    = 38,
 693                 .right_margin   = 37,
 694                 .upper_margin   = 16,
 695                 .lower_margin   = 15,
 696                 .hsync_len      = 30,
 697                 .vsync_len      = 3,
 698                 .sync           = 0,
 699                 .vmode          = FB_VMODE_NONINTERLACED
 700 } } };
 701 size_t display_count = ARRAY_SIZE(displays);
 702
 703 int board_cfb_skip(void)
 704 {
 705         return NULL != env_get("novideo");
 706 }
 707
 708 static void setup_display(void)
 709 {
 710         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 711         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 712         int reg;
 713
 714         enable_ipu_clock();
 715         imx_setup_hdmi();
 716         /* Turn on LDB0,IPU,IPU DI0 clocks */
 717         reg = __raw_readl(&mxc_ccm->CCGR3);
 718         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
 719         writel(reg, &mxc_ccm->CCGR3);
 720
 721         /* set LDB0, LDB1 clk select to 011/011 */
 722         reg = readl(&mxc_ccm->cs2cdr);
 723         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 724                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 725         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 726               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 727         writel(reg, &mxc_ccm->cs2cdr);
 728
 729         reg = readl(&mxc_ccm->cscmr2);
 730         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 731         writel(reg, &mxc_ccm->cscmr2);
 732
 733         reg = readl(&mxc_ccm->chsccdr);
 734         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 735                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 736         writel(reg, &mxc_ccm->chsccdr);
 737
 738         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 739              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 740              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 741              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 742              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 743              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 744              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 745              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 746              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 747         writel(reg, &iomux->gpr[2]);
 748
 749         reg = readl(&iomux->gpr[3]);
 750         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 751                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 752             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 753                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 754         writel(reg, &iomux->gpr[3]);
 755
 756         /* backlights off until needed */
 757         SETUP_IOMUX_PADS(backlight_pads);
 758         gpio_direction_input(LVDS_BACKLIGHT_GP);
 759         gpio_direction_input(RGB_BACKLIGHT_GP);
 760 }
 761 #endif
 762
 763 static iomux_v3_cfg_t const init_pads[] = {
 764         /* SGTL5000 sys_mclk */
 765         IOMUX_PAD_CTRL(GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
 766
 767         /* J5 - Camera MCLK */
 768         IOMUX_PAD_CTRL(GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
 769
 770         /* wl1271 pads on nitrogen6x */
 771         /* WL12XX_WL_IRQ_GP */
 772         IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 773         /* WL12XX_WL_ENABLE_GP */
 774         IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 775         /* WL12XX_BT_ENABLE_GP */
 776         IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 777         /* USB otg power */
 778         IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 779         IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
 780         IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
 781         IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
 782         IOMUX_PAD_CTRL(GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
 783 };
 784
 785 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 786
 787 static unsigned gpios_out_low[] = {
 788         /* Disable wl1271 */
 789         IMX_GPIO_NR(6, 15),     /* disable wireless */
 790         IMX_GPIO_NR(6, 16),     /* disable bluetooth */
 791         IMX_GPIO_NR(3, 22),     /* disable USB otg power */
 792         IMX_GPIO_NR(2, 5),      /* ov5640 mipi camera reset */
 793         IMX_GPIO_NR(1, 8),      /* ov5642 reset */
 794 };
 795
 796 static unsigned gpios_out_high[] = {
 797         IMX_GPIO_NR(1, 6),      /* ov5642 powerdown */
 798         IMX_GPIO_NR(6, 9),      /* ov5640 mipi camera power down */
 799 };
 800
 801 static void set_gpios(unsigned *p, int cnt, int val)
 802 {
 803         int i;
 804
 805         for (i = 0; i < cnt; i++)
 806                 gpio_direction_output(*p++, val);
 807 }
 808
 809 int board_early_init_f(void)
 810 {
 811         setup_iomux_uart();
 812
 813         set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
 814         set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
 815         gpio_direction_input(WL12XX_WL_IRQ_GP);
 816
 817         SETUP_IOMUX_PADS(wl12xx_pads);
 818         SETUP_IOMUX_PADS(init_pads);
 819         setup_buttons();
 820
 821 #if defined(CONFIG_VIDEO_IPUV3)
 822         setup_display();
 823 #endif
 824         return 0;
 825 }
 826
 827 /*
 828  * Do not overwrite the console
 829  * Use always serial for U-Boot console
 830  */
 831 int overwrite_console(void)
 832 {
 833         return 1;
 834 }
 835
 836 int board_init(void)
 837 {
 838         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 839         struct i2c_pads_info *p = i2c_pads;
 840         int i;
 841         int stride = 1;
 842
 843 #if defined(CONFIG_MX6QDL)
 844         stride = 2;
 845         if (!is_mx6dq() && !is_mx6dqp())
 846                 p += 1;
 847 #endif
 848         clrsetbits_le32(&iomuxc_regs->gpr[1],
 849                         IOMUXC_GPR1_OTG_ID_MASK,
 850                         IOMUXC_GPR1_OTG_ID_GPIO1);
 851
 852         SETUP_IOMUX_PADS(misc_pads);
 853
 854         /* address of boot parameters */
 855         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 856
 857 #ifdef CONFIG_MXC_SPI
 858         setup_spi();
 859 #endif
 860         SETUP_IOMUX_PADS(usdhc2_pads);
 861         for (i = 0; i < I2C_BUS_CNT; i++) {
 862                 setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, p);
 863                 p += stride;
 864         }
 865
 866 #ifdef CONFIG_SATA
 867         setup_sata();
 868 #endif
 869
 870         return 0;
 871 }
 872
 873 int checkboard(void)
 874 {
 875         int ret = gpio_get_value(WL12XX_WL_IRQ_GP);
 876
 877         if (ret < 0) {
 878                 /* The gpios have not been probed yet. Read it myself */
 879                 struct gpio_regs *regs = (struct gpio_regs *)GPIO6_BASE_ADDR;
 880                 int gpio = WL12XX_WL_IRQ_GP & 0x1f;
 881
 882                 ret = (readl(&regs->gpio_psr) >> gpio) & 0x01;
 883         }
 884         if (ret)
 885                 puts("Board: Nitrogen6X\n");
 886         else
 887                 puts("Board: SABRE Lite\n");
 888
 889         return 0;
 890 }
 891
 892 struct button_key {
 893         char const      *name;
 894         unsigned        gpnum;
 895         char            ident;
 896 };
 897
 898 static struct button_key const buttons[] = {
 899         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 900         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 901         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 902         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 903         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 904         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 905 };
 906
 907 /*
 908  * generate a null-terminated string containing the buttons pressed
 909  * returns number of keys pressed
 910  */
 911 static int read_keys(char *buf)
 912 {
 913         int i, numpressed = 0;
 914         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 915                 if (!gpio_get_value(buttons[i].gpnum))
 916                         buf[numpressed++] = buttons[i].ident;
 917         }
 918         buf[numpressed] = '\0';
 919         return numpressed;
 920 }
 921
 922 static int do_kbd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 923 {
 924         char envvalue[ARRAY_SIZE(buttons)+1];
 925         int numpressed = read_keys(envvalue);
 926         env_set("keybd", envvalue);
 927         return numpressed == 0;
 928 }
 929
 930 U_BOOT_CMD(
 931         kbd, 1, 1, do_kbd,
 932         "Tests for keypresses, sets 'keybd' environment variable",
 933         "Returns 0 (true) to shell if key is pressed."
 934 );
 935
 936 #ifdef CONFIG_PREBOOT
 937 static char const kbd_magic_prefix[] = "key_magic";
 938 static char const kbd_command_prefix[] = "key_cmd";
 939
 940 static void preboot_keys(void)
 941 {
 942         int numpressed;
 943         char keypress[ARRAY_SIZE(buttons)+1];
 944         numpressed = read_keys(keypress);
 945         if (numpressed) {
 946                 char *kbd_magic_keys = env_get("magic_keys");
 947                 char *suffix;
 948                 /*
 949                  * loop over all magic keys
 950                  */
 951                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
 952                         char *keys;
 953                         char magic[sizeof(kbd_magic_prefix) + 1];
 954                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
 955                         keys = env_get(magic);
 956                         if (keys) {
 957                                 if (!strcmp(keys, keypress))
 958                                         break;
 959                         }
 960                 }
 961                 if (*suffix) {
 962                         char cmd_name[sizeof(kbd_command_prefix) + 1];
 963                         char *cmd;
 964                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
 965                         cmd = env_get(cmd_name);
 966                         if (cmd) {
 967                                 env_set("preboot", cmd);
 968                                 return;
 969                         }
 970                 }
 971         }
 972 }
 973 #endif
 974
 975 #ifdef CONFIG_CMD_BMODE
 976 static const struct boot_mode board_boot_modes[] = {
 977         /* 4 bit bus width */
 978         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 979         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 980         {NULL,          0},
 981 };
 982 #endif
 983
 984 int misc_init_r(void)
 985 {
 986         gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
 987         gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
 988         gpio_request(GP_USB_OTG_PWR, "usbotg power");
 989         gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset");
 990         gpio_request(IMX_GPIO_NR(2, 2), "back");
 991         gpio_request(IMX_GPIO_NR(2, 4), "home");
 992         gpio_request(IMX_GPIO_NR(2, 1), "menu");
 993         gpio_request(IMX_GPIO_NR(2, 3), "search");
 994         gpio_request(IMX_GPIO_NR(7, 13), "volup");
 995         gpio_request(IMX_GPIO_NR(4, 5), "voldown");
 996 #ifdef CONFIG_PREBOOT
 997         preboot_keys();
 998 #endif
 999
1000 #ifdef CONFIG_CMD_BMODE
1001         add_board_boot_modes(board_boot_modes);
1002 #endif
1003         env_set_hex("reset_cause", get_imx_reset_cause());
1004         return 0;
1005 }