board/boundary/nitrogen6x/nitrogen6x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  */
   6
   7 #include <common.h>
   8 #include <env.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <malloc.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <linux/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/mxc_i2c.h>
  20 #include <asm/mach-imx/sata.h>
  21 #include <asm/mach-imx/spi.h>
  22 #include <asm/mach-imx/boot_mode.h>
  23 #include <asm/mach-imx/video.h>
  24 #include <mmc.h>
  25 #include <fsl_esdhc_imx.h>
  26 #include <micrel.h>
  27 #include <miiphy.h>
  28 #include <netdev.h>
  29 #include <asm/arch/crm_regs.h>
  30 #include <asm/arch/mxc_hdmi.h>
  31 #include <i2c.h>
  32 #include <input.h>
  33 #include <netdev.h>
  34 #include <usb/ehci-ci.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  38
  39 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  40         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  41         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  42
  43 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  44         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  45         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  46
  47 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  48         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  49
  50 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  51         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  52
  53 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  54         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  55
  56 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  58         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  59
  60 #define RGB_PAD_CTRL    PAD_CTL_DSE_120ohm
  61
  62 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  63         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  64         PAD_CTL_SRE_SLOW)
  65
  66 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  67         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  68         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  69
  70 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  71
  72 /* Prevent compiler error if gpio number 08 or 09 is used */
  73 #define not_octal(gp) ((((0x##gp >> 4) & 0xf) * 10) + ((0x##gp & 0xf)))
  74
  75 #define _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,             \
  76                 sda_pad, sda_bank, sda_gp, pad_ctrl, join_io) {                \
  77         .scl = {                                                               \
  78                 .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##scl_pad##__##i2cnum##_SCL,\
  79                                          pad_ctrl),                            \
  80                 .gpio_mode = NEW_PAD_CTRL(                                     \
  81                         cpu##_PAD_##scl_pad##__GPIO##scl_bank##join_io##scl_gp,\
  82                         pad_ctrl),                                             \
  83                 .gp = IMX_GPIO_NR(scl_bank, not_octal(scl_gp))                 \
  84         },                                                                     \
  85         .sda = {                                                               \
  86                 .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##sda_pad##__##i2cnum##_SDA,\
  87                                          pad_ctrl),                            \
  88                 .gpio_mode = NEW_PAD_CTRL(                                     \
  89                         cpu##_PAD_##sda_pad##__GPIO##sda_bank##join_io##sda_gp,\
  90                         pad_ctrl),                                             \
  91                         .gp = IMX_GPIO_NR(sda_bank, not_octal(sda_gp))         \
  92         }                                                                      \
  93 }
  94
  95 #define I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,              \
  96                 sda_pad, sda_bank, sda_gp, pad_ctrl)                           \
  97                 _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,     \
  98                                 sda_pad, sda_bank, sda_gp, pad_ctrl, _IO)
  99
 100 #if defined(CONFIG_MX6QDL)
 101 #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp,          \
 102                 sda_pad, sda_bank, sda_gp, pad_ctrl)                    \
 103         I2C_PADS_INFO_CPU(MX6Q, i2cnum, scl_pad, scl_bank, scl_gp,      \
 104                 sda_pad, sda_bank, sda_gp, pad_ctrl),                   \
 105         I2C_PADS_INFO_CPU(MX6DL, i2cnum, scl_pad, scl_bank, scl_gp,     \
 106                 sda_pad, sda_bank, sda_gp, pad_ctrl)
 107 #define I2C_PADS_INFO_ENTRY_SPACING 2
 108
 109 #define IOMUX_PAD_CTRL(name, pad_ctrl) \
 110                 NEW_PAD_CTRL(MX6Q_PAD_##name, pad_ctrl),        \
 111                 NEW_PAD_CTRL(MX6DL_PAD_##name, pad_ctrl)
 112 #else
 113 #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp,          \
 114                 sda_pad, sda_bank, sda_gp, pad_ctrl)                    \
 115         I2C_PADS_INFO_CPU(MX6, i2cnum, scl_pad, scl_bank, scl_gp,       \
 116                 sda_pad, sda_bank, sda_gp, pad_ctrl)
 117 #define I2C_PADS_INFO_ENTRY_SPACING 1
 118
 119 #define IOMUX_PAD_CTRL(name, pad_ctrl) NEW_PAD_CTRL(MX6_PAD_##name, pad_ctrl)
 120 #endif
 121
 122 int dram_init(void)
 123 {
 124         gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
 125
 126         return 0;
 127 }
 128
 129 static iomux_v3_cfg_t const uart1_pads[] = {
 130         IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
 131         IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
 132 };
 133
 134 static iomux_v3_cfg_t const uart2_pads[] = {
 135         IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
 136         IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
 137 };
 138
 139 static struct i2c_pads_info i2c_pads[] = {
 140         /* I2C1, SGTL5000 */
 141         I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
 142         /* I2C2 Camera, MIPI */
 143         I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13,
 144                             I2C_PAD_CTRL),
 145         /* I2C3, J15 - RGB connector */
 146         I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
 147 };
 148
 149 #define I2C_BUS_CNT    3
 150
 151 static iomux_v3_cfg_t const usdhc2_pads[] = {
 152         IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
 153         IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
 154         IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
 155         IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
 156         IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
 157         IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
 158 };
 159
 160 static iomux_v3_cfg_t const usdhc3_pads[] = {
 161         IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
 162         IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
 163         IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
 164         IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
 165         IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
 166         IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
 167         IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, NO_PAD_CTRL), /* CD */
 168 };
 169
 170 static iomux_v3_cfg_t const usdhc4_pads[] = {
 171         IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
 172         IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
 173         IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
 174         IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
 175         IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
 176         IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
 177         IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, NO_PAD_CTRL), /* CD */
 178 };
 179
 180 static iomux_v3_cfg_t const enet_pads1[] = {
 181         IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
 182         IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
 183         IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL),
 184         IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
 185         IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
 186         IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
 187         IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
 188         IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
 189         IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL),
 190         /* pin 35 - 1 (PHY_AD2) on reset */
 191         IOMUX_PAD_CTRL(RGMII_RXC__GPIO6_IO30, NO_PAD_CTRL),
 192         /* pin 32 - 1 - (MODE0) all */
 193         IOMUX_PAD_CTRL(RGMII_RD0__GPIO6_IO25, NO_PAD_CTRL),
 194         /* pin 31 - 1 - (MODE1) all */
 195         IOMUX_PAD_CTRL(RGMII_RD1__GPIO6_IO27, NO_PAD_CTRL),
 196         /* pin 28 - 1 - (MODE2) all */
 197         IOMUX_PAD_CTRL(RGMII_RD2__GPIO6_IO28, NO_PAD_CTRL),
 198         /* pin 27 - 1 - (MODE3) all */
 199         IOMUX_PAD_CTRL(RGMII_RD3__GPIO6_IO29, NO_PAD_CTRL),
 200         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 201         IOMUX_PAD_CTRL(RGMII_RX_CTL__GPIO6_IO24, NO_PAD_CTRL),
 202         /* pin 42 PHY nRST */
 203         IOMUX_PAD_CTRL(EIM_D23__GPIO3_IO23, NO_PAD_CTRL),
 204         IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, NO_PAD_CTRL),
 205 };
 206
 207 static iomux_v3_cfg_t const enet_pads2[] = {
 208         IOMUX_PAD_CTRL(RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL),
 209         IOMUX_PAD_CTRL(RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL),
 210         IOMUX_PAD_CTRL(RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL),
 211         IOMUX_PAD_CTRL(RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL),
 212         IOMUX_PAD_CTRL(RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL),
 213         IOMUX_PAD_CTRL(RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL),
 214 };
 215
 216 static iomux_v3_cfg_t const misc_pads[] = {
 217         IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
 218         IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
 219         IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
 220         /* OTG Power enable */
 221         IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 222 };
 223
 224 /* wl1271 pads on nitrogen6x */
 225 static iomux_v3_cfg_t const wl12xx_pads[] = {
 226         IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 227         IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 228         IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 229 };
 230 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 231 #define WL12XX_WL_ENABLE_GP     IMX_GPIO_NR(6, 15)
 232 #define WL12XX_BT_ENABLE_GP     IMX_GPIO_NR(6, 16)
 233
 234 /* Button assignments for J14 */
 235 static iomux_v3_cfg_t const button_pads[] = {
 236         /* Menu */
 237         IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, BUTTON_PAD_CTRL),
 238         /* Back */
 239         IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, BUTTON_PAD_CTRL),
 240         /* Labelled Search (mapped to Power under Android) */
 241         IOMUX_PAD_CTRL(NANDF_D3__GPIO2_IO03, BUTTON_PAD_CTRL),
 242         /* Home */
 243         IOMUX_PAD_CTRL(NANDF_D4__GPIO2_IO04, BUTTON_PAD_CTRL),
 244         /* Volume Down */
 245         IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, BUTTON_PAD_CTRL),
 246         /* Volume Up */
 247         IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, BUTTON_PAD_CTRL),
 248 };
 249
 250 static void setup_iomux_enet(void)
 251 {
 252         gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
 253         gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
 254         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 255         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 256         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 257         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 258         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 259         SETUP_IOMUX_PADS(enet_pads1);
 260         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 261
 262         /* Need delay 10ms according to KSZ9021 spec */
 263         udelay(1000 * 10);
 264         gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
 265         gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
 266
 267         SETUP_IOMUX_PADS(enet_pads2);
 268         udelay(100);    /* Wait 100 us before using mii interface */
 269 }
 270
 271 static iomux_v3_cfg_t const usb_pads[] = {
 272         IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, NO_PAD_CTRL),
 273 };
 274
 275 static void setup_iomux_uart(void)
 276 {
 277         SETUP_IOMUX_PADS(uart1_pads);
 278         SETUP_IOMUX_PADS(uart2_pads);
 279 }
 280
 281 #ifdef CONFIG_USB_EHCI_MX6
 282 int board_ehci_hcd_init(int port)
 283 {
 284         SETUP_IOMUX_PADS(usb_pads);
 285
 286         /* Reset USB hub */
 287         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 288         mdelay(2);
 289         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 290
 291         return 0;
 292 }
 293
 294 int board_ehci_power(int port, int on)
 295 {
 296         if (port)
 297                 return 0;
 298         gpio_set_value(GP_USB_OTG_PWR, on);
 299         return 0;
 300 }
 301
 302 #endif
 303
 304 #ifdef CONFIG_FSL_ESDHC_IMX
 305 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 306         {USDHC3_BASE_ADDR},
 307         {USDHC4_BASE_ADDR},
 308 };
 309
 310 int board_mmc_getcd(struct mmc *mmc)
 311 {
 312         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 313         int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
 314                         IMX_GPIO_NR(2, 6);
 315
 316         gpio_direction_input(gp_cd);
 317         return !gpio_get_value(gp_cd);
 318 }
 319
 320 int board_mmc_init(bd_t *bis)
 321 {
 322         int ret;
 323         u32 index = 0;
 324
 325         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 326         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 327
 328         usdhc_cfg[0].max_bus_width = 4;
 329         usdhc_cfg[1].max_bus_width = 4;
 330
 331         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 332                 switch (index) {
 333                 case 0:
 334                         SETUP_IOMUX_PADS(usdhc3_pads);
 335                         break;
 336                 case 1:
 337                        SETUP_IOMUX_PADS(usdhc4_pads);
 338                        break;
 339                 default:
 340                        printf("Warning: you configured more USDHC controllers"
 341                                "(%d) then supported by the board (%d)\n",
 342                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 343                        return -EINVAL;
 344                 }
 345
 346                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 347                 if (ret)
 348                         return ret;
 349         }
 350
 351         return 0;
 352 }
 353 #endif
 354
 355 #ifdef CONFIG_MXC_SPI
 356 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 357 {
 358         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 359 }
 360
 361 static iomux_v3_cfg_t const ecspi1_pads[] = {
 362         /* SS1 */
 363         IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, NO_PAD_CTRL),
 364         IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
 365         IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
 366         IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
 367 };
 368
 369 static void setup_spi(void)
 370 {
 371         SETUP_IOMUX_PADS(ecspi1_pads);
 372 }
 373 #endif
 374
 375 int board_phy_config(struct phy_device *phydev)
 376 {
 377         /* min rx data delay */
 378         ksz9021_phy_extended_write(phydev,
 379                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 380         /* min tx data delay */
 381         ksz9021_phy_extended_write(phydev,
 382                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 383         /* max rx/tx clock delay, min rx/tx control */
 384         ksz9021_phy_extended_write(phydev,
 385                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 386         if (phydev->drv->config)
 387                 phydev->drv->config(phydev);
 388
 389         return 0;
 390 }
 391
 392 int board_eth_init(bd_t *bis)
 393 {
 394         uint32_t base = IMX_FEC_BASE;
 395         struct mii_dev *bus = NULL;
 396         struct phy_device *phydev = NULL;
 397         int ret;
 398
 399         gpio_request(WL12XX_WL_IRQ_GP, "wifi_irq");
 400         gpio_request(IMX_GPIO_NR(6, 30), "rgmii_rxc");
 401         gpio_request(IMX_GPIO_NR(6, 25), "rgmii_rd0");
 402         gpio_request(IMX_GPIO_NR(6, 27), "rgmii_rd1");
 403         gpio_request(IMX_GPIO_NR(6, 28), "rgmii_rd2");
 404         gpio_request(IMX_GPIO_NR(6, 29), "rgmii_rd3");
 405         gpio_request(IMX_GPIO_NR(6, 24), "rgmii_rx_ctl");
 406         gpio_request(IMX_GPIO_NR(3, 23), "rgmii_reset_sabrelite");
 407         gpio_request(IMX_GPIO_NR(1, 27), "rgmii_reset_nitrogen6x");
 408         setup_iomux_enet();
 409
 410 #ifdef CONFIG_FEC_MXC
 411         bus = fec_get_miibus(base, -1);
 412         if (!bus)
 413                 return -EINVAL;
 414         /* scan phy 4,5,6,7 */
 415         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 416         if (!phydev) {
 417                 ret = -EINVAL;
 418                 goto free_bus;
 419         }
 420         printf("using phy at %d\n", phydev->addr);
 421         ret  = fec_probe(bis, -1, base, bus, phydev);
 422         if (ret)
 423                 goto free_phydev;
 424 #endif
 425
 426 #ifdef CONFIG_CI_UDC
 427         /* For otg ethernet*/
 428         usb_eth_initialize(bis);
 429 #endif
 430         return 0;
 431
 432 free_phydev:
 433         free(phydev);
 434 free_bus:
 435         free(bus);
 436         return ret;
 437 }
 438
 439 static void setup_buttons(void)
 440 {
 441         SETUP_IOMUX_PADS(button_pads);
 442 }
 443
 444 #if defined(CONFIG_VIDEO_IPUV3)
 445
 446 static iomux_v3_cfg_t const backlight_pads[] = {
 447         /* Backlight on RGB connector: J15 */
 448         IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, NO_PAD_CTRL),
 449 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 450
 451         /* Backlight on LVDS connector: J6 */
 452         IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, NO_PAD_CTRL),
 453 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 454 };
 455
 456 static iomux_v3_cfg_t const rgb_pads[] = {
 457         IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
 458         IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL),
 459         IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL),
 460         IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL),
 461         IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, RGB_PAD_CTRL),
 462         IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
 463         IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
 464         IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
 465         IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
 466         IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
 467         IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL),
 468         IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL),
 469         IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL),
 470         IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL),
 471         IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL),
 472         IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL),
 473         IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL),
 474         IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL),
 475         IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL),
 476         IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL),
 477         IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL),
 478         IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL),
 479         IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL),
 480         IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL),
 481         IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL),
 482         IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL),
 483         IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL),
 484         IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL),
 485         IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL),
 486 };
 487
 488 static void do_enable_hdmi(struct display_info_t const *dev)
 489 {
 490         imx_enable_hdmi_phy();
 491 }
 492
 493 static int detect_i2c(struct display_info_t const *dev)
 494 {
 495         return ((0 == i2c_set_bus_num(dev->bus))
 496                 &&
 497                 (0 == i2c_probe(dev->addr)));
 498 }
 499
 500 static void enable_lvds(struct display_info_t const *dev)
 501 {
 502         struct iomuxc *iomux = (struct iomuxc *)
 503                                 IOMUXC_BASE_ADDR;
 504         u32 reg = readl(&iomux->gpr[2]);
 505         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 506         writel(reg, &iomux->gpr[2]);
 507         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 508 }
 509
 510 static void enable_lvds_jeida(struct display_info_t const *dev)
 511 {
 512         struct iomuxc *iomux = (struct iomuxc *)
 513                                 IOMUXC_BASE_ADDR;
 514         u32 reg = readl(&iomux->gpr[2]);
 515         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 516              |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
 517         writel(reg, &iomux->gpr[2]);
 518         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 519 }
 520
 521 static void enable_rgb(struct display_info_t const *dev)
 522 {
 523         SETUP_IOMUX_PADS(rgb_pads);
 524         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 525 }
 526
 527 struct display_info_t const displays[] = {{
 528         .bus    = 1,
 529         .addr   = 0x50,
 530         .pixfmt = IPU_PIX_FMT_RGB24,
 531         .detect = detect_i2c,
 532         .enable = do_enable_hdmi,
 533         .mode   = {
 534                 .name           = "HDMI",
 535                 .refresh        = 60,
 536                 .xres           = 1024,
 537                 .yres           = 768,
 538                 .pixclock       = 15385,
 539                 .left_margin    = 220,
 540                 .right_margin   = 40,
 541                 .upper_margin   = 21,
 542                 .lower_margin   = 7,
 543                 .hsync_len      = 60,
 544                 .vsync_len      = 10,
 545                 .sync           = FB_SYNC_EXT,
 546                 .vmode          = FB_VMODE_NONINTERLACED
 547 } }, {
 548         .bus    = 0,
 549         .addr   = 0,
 550         .pixfmt = IPU_PIX_FMT_RGB24,
 551         .detect = NULL,
 552         .enable = enable_lvds_jeida,
 553         .mode   = {
 554                 .name           = "LDB-WXGA",
 555                 .refresh        = 60,
 556                 .xres           = 1280,
 557                 .yres           = 800,
 558                 .pixclock       = 14065,
 559                 .left_margin    = 40,
 560                 .right_margin   = 40,
 561                 .upper_margin   = 3,
 562                 .lower_margin   = 80,
 563                 .hsync_len      = 10,
 564                 .vsync_len      = 10,
 565                 .sync           = FB_SYNC_EXT,
 566                 .vmode          = FB_VMODE_NONINTERLACED
 567 } }, {
 568         .bus    = 0,
 569         .addr   = 0,
 570         .pixfmt = IPU_PIX_FMT_RGB24,
 571         .detect = NULL,
 572         .enable = enable_lvds,
 573         .mode   = {
 574                 .name           = "LDB-WXGA-S",
 575                 .refresh        = 60,
 576                 .xres           = 1280,
 577                 .yres           = 800,
 578                 .pixclock       = 14065,
 579                 .left_margin    = 40,
 580                 .right_margin   = 40,
 581                 .upper_margin   = 3,
 582                 .lower_margin   = 80,
 583                 .hsync_len      = 10,
 584                 .vsync_len      = 10,
 585                 .sync           = FB_SYNC_EXT,
 586                 .vmode          = FB_VMODE_NONINTERLACED
 587 } }, {
 588         .bus    = 2,
 589         .addr   = 0x4,
 590         .pixfmt = IPU_PIX_FMT_LVDS666,
 591         .detect = detect_i2c,
 592         .enable = enable_lvds,
 593         .mode   = {
 594                 .name           = "Hannstar-XGA",
 595                 .refresh        = 60,
 596                 .xres           = 1024,
 597                 .yres           = 768,
 598                 .pixclock       = 15385,
 599                 .left_margin    = 220,
 600                 .right_margin   = 40,
 601                 .upper_margin   = 21,
 602                 .lower_margin   = 7,
 603                 .hsync_len      = 60,
 604                 .vsync_len      = 10,
 605                 .sync           = FB_SYNC_EXT,
 606                 .vmode          = FB_VMODE_NONINTERLACED
 607 } }, {
 608         .bus    = 0,
 609         .addr   = 0,
 610         .pixfmt = IPU_PIX_FMT_LVDS666,
 611         .detect = NULL,
 612         .enable = enable_lvds,
 613         .mode   = {
 614                 .name           = "LG-9.7",
 615                 .refresh        = 60,
 616                 .xres           = 1024,
 617                 .yres           = 768,
 618                 .pixclock       = 15385, /* ~65MHz */
 619                 .left_margin    = 480,
 620                 .right_margin   = 260,
 621                 .upper_margin   = 16,
 622                 .lower_margin   = 6,
 623                 .hsync_len      = 250,
 624                 .vsync_len      = 10,
 625                 .sync           = FB_SYNC_EXT,
 626                 .vmode          = FB_VMODE_NONINTERLACED
 627 } }, {
 628         .bus    = 2,
 629         .addr   = 0x38,
 630         .pixfmt = IPU_PIX_FMT_LVDS666,
 631         .detect = detect_i2c,
 632         .enable = enable_lvds,
 633         .mode   = {
 634                 .name           = "wsvga-lvds",
 635                 .refresh        = 60,
 636                 .xres           = 1024,
 637                 .yres           = 600,
 638                 .pixclock       = 15385,
 639                 .left_margin    = 220,
 640                 .right_margin   = 40,
 641                 .upper_margin   = 21,
 642                 .lower_margin   = 7,
 643                 .hsync_len      = 60,
 644                 .vsync_len      = 10,
 645                 .sync           = FB_SYNC_EXT,
 646                 .vmode          = FB_VMODE_NONINTERLACED
 647 } }, {
 648         .bus    = 2,
 649         .addr   = 0x10,
 650         .pixfmt = IPU_PIX_FMT_RGB666,
 651         .detect = detect_i2c,
 652         .enable = enable_rgb,
 653         .mode   = {
 654                 .name           = "fusion7",
 655                 .refresh        = 60,
 656                 .xres           = 800,
 657                 .yres           = 480,
 658                 .pixclock       = 33898,
 659                 .left_margin    = 96,
 660                 .right_margin   = 24,
 661                 .upper_margin   = 3,
 662                 .lower_margin   = 10,
 663                 .hsync_len      = 72,
 664                 .vsync_len      = 7,
 665                 .sync           = 0x40000002,
 666                 .vmode          = FB_VMODE_NONINTERLACED
 667 } }, {
 668         .bus    = 0,
 669         .addr   = 0,
 670         .pixfmt = IPU_PIX_FMT_RGB666,
 671         .detect = NULL,
 672         .enable = enable_rgb,
 673         .mode   = {
 674                 .name           = "svga",
 675                 .refresh        = 60,
 676                 .xres           = 800,
 677                 .yres           = 600,
 678                 .pixclock       = 15385,
 679                 .left_margin    = 220,
 680                 .right_margin   = 40,
 681                 .upper_margin   = 21,
 682                 .lower_margin   = 7,
 683                 .hsync_len      = 60,
 684                 .vsync_len      = 10,
 685                 .sync           = 0,
 686                 .vmode          = FB_VMODE_NONINTERLACED
 687 } }, {
 688         .bus    = 2,
 689         .addr   = 0x41,
 690         .pixfmt = IPU_PIX_FMT_LVDS666,
 691         .detect = detect_i2c,
 692         .enable = enable_lvds,
 693         .mode   = {
 694                 .name           = "amp1024x600",
 695                 .refresh        = 60,
 696                 .xres           = 1024,
 697                 .yres           = 600,
 698                 .pixclock       = 15385,
 699                 .left_margin    = 220,
 700                 .right_margin   = 40,
 701                 .upper_margin   = 21,
 702                 .lower_margin   = 7,
 703                 .hsync_len      = 60,
 704                 .vsync_len      = 10,
 705                 .sync           = FB_SYNC_EXT,
 706                 .vmode          = FB_VMODE_NONINTERLACED
 707 } }, {
 708         .bus    = 0,
 709         .addr   = 0,
 710         .pixfmt = IPU_PIX_FMT_LVDS666,
 711         .detect = 0,
 712         .enable = enable_lvds,
 713         .mode   = {
 714                 .name           = "wvga-lvds",
 715                 .refresh        = 57,
 716                 .xres           = 800,
 717                 .yres           = 480,
 718                 .pixclock       = 15385,
 719                 .left_margin    = 220,
 720                 .right_margin   = 40,
 721                 .upper_margin   = 21,
 722                 .lower_margin   = 7,
 723                 .hsync_len      = 60,
 724                 .vsync_len      = 10,
 725                 .sync           = FB_SYNC_EXT,
 726                 .vmode          = FB_VMODE_NONINTERLACED
 727 } }, {
 728         .bus    = 2,
 729         .addr   = 0x48,
 730         .pixfmt = IPU_PIX_FMT_RGB666,
 731         .detect = detect_i2c,
 732         .enable = enable_rgb,
 733         .mode   = {
 734                 .name           = "wvga-rgb",
 735                 .refresh        = 57,
 736                 .xres           = 800,
 737                 .yres           = 480,
 738                 .pixclock       = 37037,
 739                 .left_margin    = 40,
 740                 .right_margin   = 60,
 741                 .upper_margin   = 10,
 742                 .lower_margin   = 10,
 743                 .hsync_len      = 20,
 744                 .vsync_len      = 10,
 745                 .sync           = 0,
 746                 .vmode          = FB_VMODE_NONINTERLACED
 747 } }, {
 748         .bus    = 0,
 749         .addr   = 0,
 750         .pixfmt = IPU_PIX_FMT_RGB24,
 751         .detect = NULL,
 752         .enable = enable_rgb,
 753         .mode   = {
 754                 .name           = "qvga",
 755                 .refresh        = 60,
 756                 .xres           = 320,
 757                 .yres           = 240,
 758                 .pixclock       = 37037,
 759                 .left_margin    = 38,
 760                 .right_margin   = 37,
 761                 .upper_margin   = 16,
 762                 .lower_margin   = 15,
 763                 .hsync_len      = 30,
 764                 .vsync_len      = 3,
 765                 .sync           = 0,
 766                 .vmode          = FB_VMODE_NONINTERLACED
 767 } } };
 768 size_t display_count = ARRAY_SIZE(displays);
 769
 770 int board_cfb_skip(void)
 771 {
 772         return NULL != env_get("novideo");
 773 }
 774
 775 static void setup_display(void)
 776 {
 777         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 778         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 779         int reg;
 780
 781         enable_ipu_clock();
 782         imx_setup_hdmi();
 783         /* Turn on LDB0,IPU,IPU DI0 clocks */
 784         reg = __raw_readl(&mxc_ccm->CCGR3);
 785         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
 786         writel(reg, &mxc_ccm->CCGR3);
 787
 788         /* set LDB0, LDB1 clk select to 011/011 */
 789         reg = readl(&mxc_ccm->cs2cdr);
 790         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 791                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 792         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 793               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 794         writel(reg, &mxc_ccm->cs2cdr);
 795
 796         reg = readl(&mxc_ccm->cscmr2);
 797         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 798         writel(reg, &mxc_ccm->cscmr2);
 799
 800         reg = readl(&mxc_ccm->chsccdr);
 801         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 802                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 803         writel(reg, &mxc_ccm->chsccdr);
 804
 805         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 806              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 807              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 808              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 809              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 810              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 811              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 812              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 813              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 814         writel(reg, &iomux->gpr[2]);
 815
 816         reg = readl(&iomux->gpr[3]);
 817         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 818                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 819             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 820                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 821         writel(reg, &iomux->gpr[3]);
 822
 823         /* backlights off until needed */
 824         SETUP_IOMUX_PADS(backlight_pads);
 825         gpio_direction_input(LVDS_BACKLIGHT_GP);
 826         gpio_direction_input(RGB_BACKLIGHT_GP);
 827 }
 828 #endif
 829
 830 static iomux_v3_cfg_t const init_pads[] = {
 831         /* SGTL5000 sys_mclk */
 832         IOMUX_PAD_CTRL(GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
 833
 834         /* J5 - Camera MCLK */
 835         IOMUX_PAD_CTRL(GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
 836
 837         /* wl1271 pads on nitrogen6x */
 838         /* WL12XX_WL_IRQ_GP */
 839         IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 840         /* WL12XX_WL_ENABLE_GP */
 841         IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 842         /* WL12XX_BT_ENABLE_GP */
 843         IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 844         /* USB otg power */
 845         IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 846         IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
 847         IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
 848         IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
 849         IOMUX_PAD_CTRL(GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
 850 };
 851
 852 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 853
 854 static unsigned gpios_out_low[] = {
 855         /* Disable wl1271 */
 856         IMX_GPIO_NR(6, 15),     /* disable wireless */
 857         IMX_GPIO_NR(6, 16),     /* disable bluetooth */
 858         IMX_GPIO_NR(3, 22),     /* disable USB otg power */
 859         IMX_GPIO_NR(2, 5),      /* ov5640 mipi camera reset */
 860         IMX_GPIO_NR(1, 8),      /* ov5642 reset */
 861 };
 862
 863 static unsigned gpios_out_high[] = {
 864         IMX_GPIO_NR(1, 6),      /* ov5642 powerdown */
 865         IMX_GPIO_NR(6, 9),      /* ov5640 mipi camera power down */
 866 };
 867
 868 static void set_gpios(unsigned *p, int cnt, int val)
 869 {
 870         int i;
 871
 872         for (i = 0; i < cnt; i++)
 873                 gpio_direction_output(*p++, val);
 874 }
 875
 876 int board_early_init_f(void)
 877 {
 878         setup_iomux_uart();
 879
 880         set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
 881         set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
 882         gpio_direction_input(WL12XX_WL_IRQ_GP);
 883
 884         SETUP_IOMUX_PADS(wl12xx_pads);
 885         SETUP_IOMUX_PADS(init_pads);
 886         setup_buttons();
 887
 888 #if defined(CONFIG_VIDEO_IPUV3)
 889         setup_display();
 890 #endif
 891         return 0;
 892 }
 893
 894 /*
 895  * Do not overwrite the console
 896  * Use always serial for U-Boot console
 897  */
 898 int overwrite_console(void)
 899 {
 900         return 1;
 901 }
 902
 903 int board_init(void)
 904 {
 905         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 906         struct i2c_pads_info *p = i2c_pads;
 907         int i;
 908         int stride = 1;
 909
 910 #if defined(CONFIG_MX6QDL)
 911         stride = 2;
 912         if (!is_mx6dq() && !is_mx6dqp())
 913                 p += 1;
 914 #endif
 915         clrsetbits_le32(&iomuxc_regs->gpr[1],
 916                         IOMUXC_GPR1_OTG_ID_MASK,
 917                         IOMUXC_GPR1_OTG_ID_GPIO1);
 918
 919         SETUP_IOMUX_PADS(misc_pads);
 920
 921         /* address of boot parameters */
 922         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 923
 924 #ifdef CONFIG_MXC_SPI
 925         setup_spi();
 926 #endif
 927         SETUP_IOMUX_PADS(usdhc2_pads);
 928         for (i = 0; i < I2C_BUS_CNT; i++) {
 929                 setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, p);
 930                 p += stride;
 931         }
 932
 933 #ifdef CONFIG_SATA
 934         setup_sata();
 935 #endif
 936
 937         return 0;
 938 }
 939
 940 int checkboard(void)
 941 {
 942         int ret = gpio_get_value(WL12XX_WL_IRQ_GP);
 943
 944         if (ret < 0) {
 945                 /* The gpios have not been probed yet. Read it myself */
 946                 struct gpio_regs *regs = (struct gpio_regs *)GPIO6_BASE_ADDR;
 947                 int gpio = WL12XX_WL_IRQ_GP & 0x1f;
 948
 949                 ret = (readl(&regs->gpio_psr) >> gpio) & 0x01;
 950         }
 951         if (ret)
 952                 puts("Board: Nitrogen6X\n");
 953         else
 954                 puts("Board: SABRE Lite\n");
 955
 956         return 0;
 957 }
 958
 959 struct button_key {
 960         char const      *name;
 961         unsigned        gpnum;
 962         char            ident;
 963 };
 964
 965 static struct button_key const buttons[] = {
 966         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 967         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 968         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 969         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 970         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 971         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 972 };
 973
 974 /*
 975  * generate a null-terminated string containing the buttons pressed
 976  * returns number of keys pressed
 977  */
 978 static int read_keys(char *buf)
 979 {
 980         int i, numpressed = 0;
 981         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 982                 if (!gpio_get_value(buttons[i].gpnum))
 983                         buf[numpressed++] = buttons[i].ident;
 984         }
 985         buf[numpressed] = '\0';
 986         return numpressed;
 987 }
 988
 989 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 990 {
 991         char envvalue[ARRAY_SIZE(buttons)+1];
 992         int numpressed = read_keys(envvalue);
 993         env_set("keybd", envvalue);
 994         return numpressed == 0;
 995 }
 996
 997 U_BOOT_CMD(
 998         kbd, 1, 1, do_kbd,
 999         "Tests for keypresses, sets 'keybd' environment variable",
1000         "Returns 0 (true) to shell if key is pressed."
1001 );
1002
1003 #ifdef CONFIG_PREBOOT
1004 static char const kbd_magic_prefix[] = "key_magic";
1005 static char const kbd_command_prefix[] = "key_cmd";
1006
1007 static void preboot_keys(void)
1008 {
1009         int numpressed;
1010         char keypress[ARRAY_SIZE(buttons)+1];
1011         numpressed = read_keys(keypress);
1012         if (numpressed) {
1013                 char *kbd_magic_keys = env_get("magic_keys");
1014                 char *suffix;
1015                 /*
1016                  * loop over all magic keys
1017                  */
1018                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
1019                         char *keys;
1020                         char magic[sizeof(kbd_magic_prefix) + 1];
1021                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
1022                         keys = env_get(magic);
1023                         if (keys) {
1024                                 if (!strcmp(keys, keypress))
1025                                         break;
1026                         }
1027                 }
1028                 if (*suffix) {
1029                         char cmd_name[sizeof(kbd_command_prefix) + 1];
1030                         char *cmd;
1031                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
1032                         cmd = env_get(cmd_name);
1033                         if (cmd) {
1034                                 env_set("preboot", cmd);
1035                                 return;
1036                         }
1037                 }
1038         }
1039 }
1040 #endif
1041
1042 #ifdef CONFIG_CMD_BMODE
1043 static const struct boot_mode board_boot_modes[] = {
1044         /* 4 bit bus width */
1045         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
1046         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
1047         {NULL,          0},
1048 };
1049 #endif
1050
1051 int misc_init_r(void)
1052 {
1053         gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
1054         gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
1055         gpio_request(GP_USB_OTG_PWR, "usbotg power");
1056         gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset");
1057         gpio_request(IMX_GPIO_NR(2, 2), "back");
1058         gpio_request(IMX_GPIO_NR(2, 4), "home");
1059         gpio_request(IMX_GPIO_NR(2, 1), "menu");
1060         gpio_request(IMX_GPIO_NR(2, 3), "search");
1061         gpio_request(IMX_GPIO_NR(7, 13), "volup");
1062         gpio_request(IMX_GPIO_NR(4, 5), "voldown");
1063 #ifdef CONFIG_PREBOOT
1064         preboot_keys();
1065 #endif
1066
1067 #ifdef CONFIG_CMD_BMODE
1068         add_board_boot_modes(board_boot_modes);
1069 #endif
1070         env_set_hex("reset_cause", get_imx_reset_cause());
1071         return 0;
1072 }