mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a board
[kernel/u-boot.git] / board / boundary / nitrogen6x / nitrogen6x.c
1 /*
2  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23
24 #include <common.h>
25 #include <asm/io.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/imx-regs.h>
28 #include <asm/arch/iomux.h>
29 #include <asm/arch/sys_proto.h>
30 #include <malloc.h>
31 #include <asm/arch/mx6-pins.h>
32 #include <asm/errno.h>
33 #include <asm/gpio.h>
34 #include <asm/imx-common/iomux-v3.h>
35 #include <asm/imx-common/mxc_i2c.h>
36 #include <asm/imx-common/boot_mode.h>
37 #include <mmc.h>
38 #include <fsl_esdhc.h>
39 #include <micrel.h>
40 #include <miiphy.h>
41 #include <netdev.h>
42 #include <linux/fb.h>
43 #include <ipu_pixfmt.h>
44 #include <asm/arch/crm_regs.h>
45 #include <asm/arch/mxc_hdmi.h>
46 #include <i2c.h>
47
48 DECLARE_GLOBAL_DATA_PTR;
49
50 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
51         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |              \
52         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
53
54 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
55         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |              \
56         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
57
58 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
59         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
60         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
61
62 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
63         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
64         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
65
66 #define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
67         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
68         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
69
70 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
71         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
72         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
73         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
74
75 #define WEAK_PULLUP     (PAD_CTL_PKE | PAD_CTL_PUE |            \
76         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
77         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
78         PAD_CTL_SRE_SLOW)
79
80 #define WEAK_PULLDOWN   (PAD_CTL_PKE | PAD_CTL_PUE |            \
81         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
82         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
83         PAD_CTL_SRE_SLOW)
84
85 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
86
87 int dram_init(void)
88 {
89         gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
90
91         return 0;
92 }
93
94 iomux_v3_cfg_t const uart1_pads[] = {
95         MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
96         MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
97 };
98
99 iomux_v3_cfg_t const uart2_pads[] = {
100         MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
101         MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
102 };
103
104 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
105
106 /* I2C1, SGTL5000 */
107 struct i2c_pads_info i2c_pad_info0 = {
108         .scl = {
109                 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
110                 .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
111                 .gp = IMX_GPIO_NR(3, 21)
112         },
113         .sda = {
114                 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
115                 .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
116                 .gp = IMX_GPIO_NR(3, 28)
117         }
118 };
119
120 /* I2C2 Camera, MIPI */
121 struct i2c_pads_info i2c_pad_info1 = {
122         .scl = {
123                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
124                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
125                 .gp = IMX_GPIO_NR(4, 12)
126         },
127         .sda = {
128                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
129                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
130                 .gp = IMX_GPIO_NR(4, 13)
131         }
132 };
133
134 /* I2C3, J15 - RGB connector */
135 struct i2c_pads_info i2c_pad_info2 = {
136         .scl = {
137                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
138                 .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
139                 .gp = IMX_GPIO_NR(1, 5)
140         },
141         .sda = {
142                 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
143                 .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
144                 .gp = IMX_GPIO_NR(7, 11)
145         }
146 };
147
148 iomux_v3_cfg_t const usdhc3_pads[] = {
149         MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
150         MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151         MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152         MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153         MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154         MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155         MX6_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
156 };
157
158 iomux_v3_cfg_t const usdhc4_pads[] = {
159         MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
160         MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
161         MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
162         MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
163         MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
164         MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
165         MX6_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
166 };
167
168 iomux_v3_cfg_t const enet_pads1[] = {
169         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
170         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
171         MX6_PAD_RGMII_TXC__ENET_RGMII_TXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
172         MX6_PAD_RGMII_TD0__ENET_RGMII_TD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
173         MX6_PAD_RGMII_TD1__ENET_RGMII_TD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
174         MX6_PAD_RGMII_TD2__ENET_RGMII_TD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
175         MX6_PAD_RGMII_TD3__ENET_RGMII_TD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
176         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
177         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
178         /* pin 35 - 1 (PHY_AD2) on reset */
179         MX6_PAD_RGMII_RXC__GPIO_6_30            | MUX_PAD_CTRL(NO_PAD_CTRL),
180         /* pin 32 - 1 - (MODE0) all */
181         MX6_PAD_RGMII_RD0__GPIO_6_25            | MUX_PAD_CTRL(NO_PAD_CTRL),
182         /* pin 31 - 1 - (MODE1) all */
183         MX6_PAD_RGMII_RD1__GPIO_6_27            | MUX_PAD_CTRL(NO_PAD_CTRL),
184         /* pin 28 - 1 - (MODE2) all */
185         MX6_PAD_RGMII_RD2__GPIO_6_28            | MUX_PAD_CTRL(NO_PAD_CTRL),
186         /* pin 27 - 1 - (MODE3) all */
187         MX6_PAD_RGMII_RD3__GPIO_6_29            | MUX_PAD_CTRL(NO_PAD_CTRL),
188         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
189         MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
190         /* pin 42 PHY nRST */
191         MX6_PAD_EIM_D23__GPIO_3_23              | MUX_PAD_CTRL(NO_PAD_CTRL),
192         MX6_PAD_ENET_RXD0__GPIO_1_27            | MUX_PAD_CTRL(NO_PAD_CTRL),
193 };
194
195 iomux_v3_cfg_t const enet_pads2[] = {
196         MX6_PAD_RGMII_RXC__ENET_RGMII_RXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
197         MX6_PAD_RGMII_RD0__ENET_RGMII_RD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
198         MX6_PAD_RGMII_RD1__ENET_RGMII_RD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
199         MX6_PAD_RGMII_RD2__ENET_RGMII_RD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
200         MX6_PAD_RGMII_RD3__ENET_RGMII_RD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
201         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
202 };
203
204 /* wl1271 pads on nitrogen6x */
205 iomux_v3_cfg_t const wl12xx_pads[] = {
206         (MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK)
207                 | MUX_PAD_CTRL(WEAK_PULLDOWN),
208         (MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK)
209                 | MUX_PAD_CTRL(OUTPUT_40OHM),
210         (MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK)
211                 | MUX_PAD_CTRL(OUTPUT_40OHM),
212 };
213 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
214 #define WL12XX_WL_ENABLE_GP     IMX_GPIO_NR(6, 15)
215 #define WL12XX_BT_ENABLE_GP     IMX_GPIO_NR(6, 16)
216
217 /* Button assignments for J14 */
218 static iomux_v3_cfg_t const button_pads[] = {
219         /* Menu */
220         MX6_PAD_NANDF_D1__GPIO_2_1      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
221         /* Back */
222         MX6_PAD_NANDF_D2__GPIO_2_2      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
223         /* Labelled Search (mapped to Power under Android) */
224         MX6_PAD_NANDF_D3__GPIO_2_3      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
225         /* Home */
226         MX6_PAD_NANDF_D4__GPIO_2_4      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
227         /* Volume Down */
228         MX6_PAD_GPIO_19__GPIO_4_5       | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
229         /* Volume Up */
230         MX6_PAD_GPIO_18__GPIO_7_13      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
231 };
232
233 static void setup_iomux_enet(void)
234 {
235         gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
236         gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
237         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
238         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
239         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
240         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
241         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
242         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
243         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
244
245         /* Need delay 10ms according to KSZ9021 spec */
246         udelay(1000 * 10);
247         gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
248         gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
249
250         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
251 }
252
253 iomux_v3_cfg_t const usb_pads[] = {
254         MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
255 };
256
257 static void setup_iomux_uart(void)
258 {
259         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
260         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
261 }
262
263 #ifdef CONFIG_USB_EHCI_MX6
264 int board_ehci_hcd_init(int port)
265 {
266         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
267
268         /* Reset USB hub */
269         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
270         mdelay(2);
271         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
272
273         return 0;
274 }
275 #endif
276
277 #ifdef CONFIG_FSL_ESDHC
278 struct fsl_esdhc_cfg usdhc_cfg[2] = {
279         {USDHC3_BASE_ADDR},
280         {USDHC4_BASE_ADDR},
281 };
282
283 int board_mmc_getcd(struct mmc *mmc)
284 {
285         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
286         int ret;
287
288         if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
289                 gpio_direction_input(IMX_GPIO_NR(7, 0));
290                 ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
291         } else {
292                 gpio_direction_input(IMX_GPIO_NR(2, 6));
293                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
294         }
295
296         return ret;
297 }
298
299 int board_mmc_init(bd_t *bis)
300 {
301         s32 status = 0;
302         u32 index = 0;
303
304         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
305         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
306
307         usdhc_cfg[0].max_bus_width = 4;
308         usdhc_cfg[1].max_bus_width = 4;
309
310         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
311                 switch (index) {
312                 case 0:
313                         imx_iomux_v3_setup_multiple_pads(
314                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
315                         break;
316                 case 1:
317                        imx_iomux_v3_setup_multiple_pads(
318                                usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
319                        break;
320                 default:
321                        printf("Warning: you configured more USDHC controllers"
322                                "(%d) then supported by the board (%d)\n",
323                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
324                        return status;
325                 }
326
327                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
328         }
329
330         return status;
331 }
332 #endif
333
334 u32 get_board_rev(void)
335 {
336         return 0x63000;
337 }
338
339 #ifdef CONFIG_MXC_SPI
340 iomux_v3_cfg_t const ecspi1_pads[] = {
341         /* SS1 */
342         MX6_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
343         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
344         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
345         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
346 };
347
348 void setup_spi(void)
349 {
350         gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
351         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
352                                          ARRAY_SIZE(ecspi1_pads));
353 }
354 #endif
355
356 int board_phy_config(struct phy_device *phydev)
357 {
358         /* min rx data delay */
359         ksz9021_phy_extended_write(phydev,
360                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
361         /* min tx data delay */
362         ksz9021_phy_extended_write(phydev,
363                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
364         /* max rx/tx clock delay, min rx/tx control */
365         ksz9021_phy_extended_write(phydev,
366                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
367         if (phydev->drv->config)
368                 phydev->drv->config(phydev);
369
370         return 0;
371 }
372
373 int board_eth_init(bd_t *bis)
374 {
375         uint32_t base = IMX_FEC_BASE;
376         struct mii_dev *bus = NULL;
377         struct phy_device *phydev = NULL;
378         int ret;
379
380         setup_iomux_enet();
381
382 #ifdef CONFIG_FEC_MXC
383         bus = fec_get_miibus(base, -1);
384         if (!bus)
385                 return 0;
386         /* scan phy 4,5,6,7 */
387         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
388         if (!phydev) {
389                 free(bus);
390                 return 0;
391         }
392         printf("using phy at %d\n", phydev->addr);
393         ret  = fec_probe(bis, -1, base, bus, phydev);
394         if (ret) {
395                 printf("FEC MXC: %s:failed\n", __func__);
396                 free(phydev);
397                 free(bus);
398         }
399 #endif
400         return 0;
401 }
402
403 static void setup_buttons(void)
404 {
405         imx_iomux_v3_setup_multiple_pads(button_pads,
406                                          ARRAY_SIZE(button_pads));
407 }
408
409 #ifdef CONFIG_CMD_SATA
410
411 int setup_sata(void)
412 {
413         struct iomuxc_base_regs *const iomuxc_regs
414                 = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
415         int ret = enable_sata_clock();
416         if (ret)
417                 return ret;
418
419         clrsetbits_le32(&iomuxc_regs->gpr[13],
420                         IOMUXC_GPR13_SATA_MASK,
421                         IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
422                         |IOMUXC_GPR13_SATA_PHY_7_SATA2M
423                         |IOMUXC_GPR13_SATA_SPEED_3G
424                         |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
425                         |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
426                         |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
427                         |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
428                         |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
429                         |IOMUXC_GPR13_SATA_PHY_1_SLOW);
430
431         return 0;
432 }
433 #endif
434
435 #if defined(CONFIG_VIDEO_IPUV3)
436
437 static iomux_v3_cfg_t const backlight_pads[] = {
438         /* Backlight on RGB connector: J15 */
439         MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
440 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
441
442         /* Backlight on LVDS connector: J6 */
443         MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
444 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
445 };
446
447 static iomux_v3_cfg_t const rgb_pads[] = {
448         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
449         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
450         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
451         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
452         MX6_PAD_DI0_PIN4__GPIO_4_20,
453         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
454         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
455         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
456         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
457         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
458         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
459         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
460         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
461         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
462         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
463         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
464         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
465         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
466         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
467         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
468         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
469         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
470         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
471         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
472         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
473         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
474         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
475         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
476         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
477 };
478
479 struct display_info_t {
480         int     bus;
481         int     addr;
482         int     pixfmt;
483         int     (*detect)(struct display_info_t const *dev);
484         void    (*enable)(struct display_info_t const *dev);
485         struct  fb_videomode mode;
486 };
487
488
489 static int detect_hdmi(struct display_info_t const *dev)
490 {
491         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
492         return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
493 }
494
495 static void enable_hdmi(struct display_info_t const *dev)
496 {
497         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
498         u8 reg;
499         printf("%s: setup HDMI monitor\n", __func__);
500         reg = readb(&hdmi->phy_conf0);
501         reg |= HDMI_PHY_CONF0_PDZ_MASK;
502         writeb(reg, &hdmi->phy_conf0);
503
504         udelay(3000);
505         reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
506         writeb(reg, &hdmi->phy_conf0);
507         udelay(3000);
508         reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
509         writeb(reg, &hdmi->phy_conf0);
510         writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
511 }
512
513 static int detect_i2c(struct display_info_t const *dev)
514 {
515         return ((0 == i2c_set_bus_num(dev->bus))
516                 &&
517                 (0 == i2c_probe(dev->addr)));
518 }
519
520 static void enable_lvds(struct display_info_t const *dev)
521 {
522         struct iomuxc *iomux = (struct iomuxc *)
523                                 IOMUXC_BASE_ADDR;
524         u32 reg = readl(&iomux->gpr[2]);
525         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
526         writel(reg, &iomux->gpr[2]);
527         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
528 }
529
530 static void enable_rgb(struct display_info_t const *dev)
531 {
532         imx_iomux_v3_setup_multiple_pads(
533                 rgb_pads,
534                  ARRAY_SIZE(rgb_pads));
535         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
536 }
537
538 static struct display_info_t const displays[] = {{
539         .bus    = -1,
540         .addr   = 0,
541         .pixfmt = IPU_PIX_FMT_RGB24,
542         .detect = detect_hdmi,
543         .enable = enable_hdmi,
544         .mode   = {
545                 .name           = "HDMI",
546                 .refresh        = 60,
547                 .xres           = 1024,
548                 .yres           = 768,
549                 .pixclock       = 15385,
550                 .left_margin    = 220,
551                 .right_margin   = 40,
552                 .upper_margin   = 21,
553                 .lower_margin   = 7,
554                 .hsync_len      = 60,
555                 .vsync_len      = 10,
556                 .sync           = FB_SYNC_EXT,
557                 .vmode          = FB_VMODE_NONINTERLACED
558 } }, {
559         .bus    = 2,
560         .addr   = 0x4,
561         .pixfmt = IPU_PIX_FMT_LVDS666,
562         .detect = detect_i2c,
563         .enable = enable_lvds,
564         .mode   = {
565                 .name           = "Hannstar-XGA",
566                 .refresh        = 60,
567                 .xres           = 1024,
568                 .yres           = 768,
569                 .pixclock       = 15385,
570                 .left_margin    = 220,
571                 .right_margin   = 40,
572                 .upper_margin   = 21,
573                 .lower_margin   = 7,
574                 .hsync_len      = 60,
575                 .vsync_len      = 10,
576                 .sync           = FB_SYNC_EXT,
577                 .vmode          = FB_VMODE_NONINTERLACED
578 } }, {
579         .bus    = 2,
580         .addr   = 0x38,
581         .pixfmt = IPU_PIX_FMT_LVDS666,
582         .detect = detect_i2c,
583         .enable = enable_lvds,
584         .mode   = {
585                 .name           = "wsvga-lvds",
586                 .refresh        = 60,
587                 .xres           = 1024,
588                 .yres           = 600,
589                 .pixclock       = 15385,
590                 .left_margin    = 220,
591                 .right_margin   = 40,
592                 .upper_margin   = 21,
593                 .lower_margin   = 7,
594                 .hsync_len      = 60,
595                 .vsync_len      = 10,
596                 .sync           = FB_SYNC_EXT,
597                 .vmode          = FB_VMODE_NONINTERLACED
598 } }, {
599         .bus    = 2,
600         .addr   = 0x48,
601         .pixfmt = IPU_PIX_FMT_RGB666,
602         .detect = detect_i2c,
603         .enable = enable_rgb,
604         .mode   = {
605                 .name           = "wvga-rgb",
606                 .refresh        = 57,
607                 .xres           = 800,
608                 .yres           = 480,
609                 .pixclock       = 37037,
610                 .left_margin    = 40,
611                 .right_margin   = 60,
612                 .upper_margin   = 10,
613                 .lower_margin   = 10,
614                 .hsync_len      = 20,
615                 .vsync_len      = 10,
616                 .sync           = 0,
617                 .vmode          = FB_VMODE_NONINTERLACED
618 } } };
619
620 int board_video_skip(void)
621 {
622         int i;
623         int ret;
624         char const *panel = getenv("panel");
625         if (!panel) {
626                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
627                         struct display_info_t const *dev = displays+i;
628                         if (dev->detect(dev)) {
629                                 panel = dev->mode.name;
630                                 printf("auto-detected panel %s\n", panel);
631                                 break;
632                         }
633                 }
634                 if (!panel) {
635                         panel = displays[0].mode.name;
636                         printf("No panel detected: default to %s\n", panel);
637                 }
638         } else {
639                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
640                         if (!strcmp(panel, displays[i].mode.name))
641                                 break;
642                 }
643         }
644         if (i < ARRAY_SIZE(displays)) {
645                 ret = ipuv3_fb_init(&displays[i].mode, 0,
646                                     displays[i].pixfmt);
647                 if (!ret) {
648                         displays[i].enable(displays+i);
649                         printf("Display: %s (%ux%u)\n",
650                                displays[i].mode.name,
651                                displays[i].mode.xres,
652                                displays[i].mode.yres);
653                 } else
654                         printf("LCD %s cannot be configured: %d\n",
655                                displays[i].mode.name, ret);
656         } else {
657                 printf("unsupported panel %s\n", panel);
658                 ret = -EINVAL;
659         }
660         return (0 != ret);
661 }
662
663 static void setup_display(void)
664 {
665         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
666         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
667         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
668         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
669
670         int reg;
671
672         /* Turn on LDB0,IPU,IPU DI0 clocks */
673         reg = __raw_readl(&mxc_ccm->CCGR3);
674         reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
675                 |MXC_CCM_CCGR3_LDB_DI0_MASK;
676         writel(reg, &mxc_ccm->CCGR3);
677
678         /* Turn on HDMI PHY clock */
679         reg = __raw_readl(&mxc_ccm->CCGR2);
680         reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
681                |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
682         writel(reg, &mxc_ccm->CCGR2);
683
684         /* clear HDMI PHY reset */
685         writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
686
687         /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
688         writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
689         writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
690
691         /* set LDB0, LDB1 clk select to 011/011 */
692         reg = readl(&mxc_ccm->cs2cdr);
693         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
694                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
695         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
696               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
697         writel(reg, &mxc_ccm->cs2cdr);
698
699         reg = readl(&mxc_ccm->cscmr2);
700         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
701         writel(reg, &mxc_ccm->cscmr2);
702
703         reg = readl(&mxc_ccm->chsccdr);
704         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
705                 |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
706                 |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
707         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
708                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
709               |(CHSCCDR_PODF_DIVIDE_BY_3
710                 <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
711               |(CHSCCDR_IPU_PRE_CLK_540M_PFD
712                 <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
713         writel(reg, &mxc_ccm->chsccdr);
714
715         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
716              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
717              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
718              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
719              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
720              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
721              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
722              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
723              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
724         writel(reg, &iomux->gpr[2]);
725
726         reg = readl(&iomux->gpr[3]);
727         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
728             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
729                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
730         writel(reg, &iomux->gpr[3]);
731
732         /* backlights off until needed */
733         imx_iomux_v3_setup_multiple_pads(backlight_pads,
734                                          ARRAY_SIZE(backlight_pads));
735         gpio_direction_input(LVDS_BACKLIGHT_GP);
736         gpio_direction_input(RGB_BACKLIGHT_GP);
737 }
738 #endif
739
740 int board_early_init_f(void)
741 {
742         setup_iomux_uart();
743
744         /* Disable wl1271 For Nitrogen6w */
745         gpio_direction_input(WL12XX_WL_IRQ_GP);
746         gpio_direction_output(WL12XX_WL_ENABLE_GP, 0);
747         gpio_direction_output(WL12XX_BT_ENABLE_GP, 0);
748
749         imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
750         setup_buttons();
751
752 #if defined(CONFIG_VIDEO_IPUV3)
753         setup_display();
754 #endif
755         return 0;
756 }
757
758 /*
759  * Do not overwrite the console
760  * Use always serial for U-Boot console
761  */
762 int overwrite_console(void)
763 {
764         return 1;
765 }
766
767 int board_init(void)
768 {
769         /* address of boot parameters */
770         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
771
772 #ifdef CONFIG_MXC_SPI
773         setup_spi();
774 #endif
775         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
776         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
777         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
778
779 #ifdef CONFIG_CMD_SATA
780         setup_sata();
781 #endif
782
783         return 0;
784 }
785
786 int checkboard(void)
787 {
788         if (gpio_get_value(WL12XX_WL_IRQ_GP))
789                 puts("Board: Nitrogen6X\n");
790         else
791                 puts("Board: SABRE Lite\n");
792
793         return 0;
794 }
795
796 struct button_key {
797         char const      *name;
798         unsigned        gpnum;
799         char            ident;
800 };
801
802 static struct button_key const buttons[] = {
803         {"back",        IMX_GPIO_NR(2, 2),      'B'},
804         {"home",        IMX_GPIO_NR(2, 4),      'H'},
805         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
806         {"search",      IMX_GPIO_NR(2, 3),      'S'},
807         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
808         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
809 };
810
811 /*
812  * generate a null-terminated string containing the buttons pressed
813  * returns number of keys pressed
814  */
815 static int read_keys(char *buf)
816 {
817         int i, numpressed = 0;
818         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
819                 if (!gpio_get_value(buttons[i].gpnum))
820                         buf[numpressed++] = buttons[i].ident;
821         }
822         buf[numpressed] = '\0';
823         return numpressed;
824 }
825
826 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
827 {
828         char envvalue[ARRAY_SIZE(buttons)+1];
829         int numpressed = read_keys(envvalue);
830         setenv("keybd", envvalue);
831         return numpressed == 0;
832 }
833
834 U_BOOT_CMD(
835         kbd, 1, 1, do_kbd,
836         "Tests for keypresses, sets 'keybd' environment variable",
837         "Returns 0 (true) to shell if key is pressed."
838 );
839
840 #ifdef CONFIG_PREBOOT
841 static char const kbd_magic_prefix[] = "key_magic";
842 static char const kbd_command_prefix[] = "key_cmd";
843
844 static void preboot_keys(void)
845 {
846         int numpressed;
847         char keypress[ARRAY_SIZE(buttons)+1];
848         numpressed = read_keys(keypress);
849         if (numpressed) {
850                 char *kbd_magic_keys = getenv("magic_keys");
851                 char *suffix;
852                 /*
853                  * loop over all magic keys
854                  */
855                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
856                         char *keys;
857                         char magic[sizeof(kbd_magic_prefix) + 1];
858                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
859                         keys = getenv(magic);
860                         if (keys) {
861                                 if (!strcmp(keys, keypress))
862                                         break;
863                         }
864                 }
865                 if (*suffix) {
866                         char cmd_name[sizeof(kbd_command_prefix) + 1];
867                         char *cmd;
868                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
869                         cmd = getenv(cmd_name);
870                         if (cmd) {
871                                 setenv("preboot", cmd);
872                                 return;
873                         }
874                 }
875         }
876 }
877 #endif
878
879 #ifdef CONFIG_CMD_BMODE
880 static const struct boot_mode board_boot_modes[] = {
881         /* 4 bit bus width */
882         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
883         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
884         {NULL,          0},
885 };
886 #endif
887
888 int misc_init_r(void)
889 {
890 #ifdef CONFIG_PREBOOT
891         preboot_keys();
892 #endif
893
894 #ifdef CONFIG_CMD_BMODE
895         add_board_boot_modes(board_boot_modes);
896 #endif
897         return 0;
898 }